Omron CJ - INSTRUCTIONS

723
3. Instructions
CS/CJ/NSJ Series Instructions Reference Manual (W474)
Interrupt Control Instructions
3
CLI
(2) Setting the Time to the First Scheduled Interrupts
(3) Clearing/Retaining High-speed Counter Interrupt Causes (CJ1M or CJ2M CPU Units Only)
z Operand Specifications
C Interrupt input Control data (cause processing data)
Inputs to a CS1W-INT01 or CJ1W-INT01
Interrupt Input Unit (16 inputs/Unit)
Set to 0000 to FFFF hex.
Bits 0 to 15 correspond to each interrupt task. Individual bit settings are as follows:
0: Retain the recorded interrupt.
1: Clear the recorded interrupt.
Inputs to a C200HS-INT01 Interrupt Input
Unit (8 inputs/Unit)
Set to 0000 to 00FF hex
Bits 0 to 7 correspond to each interrupt task. Individual bit settings are as follows:
0: Retain the recorded interrupt.
1: Clear the recorded interrupt.
Inputs to a CJ1M-CPU2@ CPU Unit's Built-in
Inputs (4 inputs/Unit)
0001 hex: Clear the recorded interrupt.
0000 hex: Retain the recorded interrupt.
CJ2M CPU Unit inputs (when Pulse I/O
Module is mounted) (4 inputs/Block)
Operand Contents
N
Interrupt identifier
4: Interrupt task 0 (interrupt task 2)
5: Interrupt task 1 (interrupt task 3)
Note 1 Only scheduled interrupt 0 can be used with the CJ1M-CPU11/21.
2 The scheduled interrupts (0 and 1) cannot be used with a CJ2 CPU Unit if the synchronous unit operation function is
enabled.
C
Scheduled interrupt time units
(Set in the PLC Setup.)
Scheduled interrupt set time
10 ms 0 to 9,999 decimal (0000 to 270F hex):
Sets time to first interrupt between 10 and 99,990 ms.
1 ms 0 to 9,999 decimal (0000 to 270F hex):
Sets time to first interrupt between 1 and 9,999 ms.)
0.1 ms 0 to 9,999 decimal (0000 to 270F hex):
Sets time to first interrupt between 0.1 and 999.9 ms.)
Operand Contents
N
Interrupt identifier
10: High-speed counter input 0
11: High-speed counter input 1
12: High-speed counter input 2
13: High-speed counter input 3
C
Recorded Interrupt
0001 hex: Clear the recorded interrupt.
0000 hex: Retain the recorded interrupt.
Area
Word addresses
Indirect DM/EM
addresses
Con-
stants
Registers Flags
Pulse
bits
TR
bits
CIO WR HR AR T C DM EM
@DM
@EM
*DM
*EM
DR IR
Indirect
using IR
TK CF
N --- --- --- --- --- --- --- --- --- ---
OK
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C OKOKOKOKOKOKOKOK OK OK OK OK
Operand Contents