7 High-speed Counters
7-16
CJ2M CPU Unit Pulse I/O Module User’s Manual
Setting a high-speed counter's PV to 0 is called resetting.
There are two reset methods.
• Phase-Z Signal + Software Reset
• Software Reset
The high-speed counter's PV is reset when the phase-Z signal (reset input) turns ON while the corre-
sponding High-speed Counter Reset Bit (A531.00 to A531.03) is ON.
The CPU Unit recognizes the ON status of the High-speed Counter Reset Bit only at the beginning of
the PLC cycle during the overseeing processes. Consequently, when the Reset Bit is turned ON in the
ladder program, the phase-Z signal does not become effective until the next PLC cycle.
The high-speed counter's PV is reset when the corresponding High-speed Counter Reset Bit (A531.00
to A531.03) turns ON.
The CPU Unit recognizes the OFF-to-ON transition of the High-speed Counter Reset Bit only at the
beginning of the PLC cycle during the overseeing processes. Reset processing is performed at the
same time. The OFF-to-ON transition will not be recognized if the Reset Bit turns OFF again within the
same cycle.
Additional Information
The comparison operation can be set to stop or continue when a high-speed counter is reset.
This enables applications where the comparison operation can be restarted from a counter PV of
0 when the counter is reset.
The present value of a high-speed counter can be read in the following three ways.
7-2-3 Reset Methods
Phase-Z Signal + Software Reset
Software Reset
7-2-4 Reading the Present Value
• Value refreshed at the I/O refresh timing
→
Read PV from Auxiliary Area.
• Value updated when a ladder program is executed
→
Read PV by executing a PRV(881)
instruction.
• PV when an interrupt input occurs →
Use the software latch and read the
value from the Auxiliary Area.
One cycle
Phase Z
Reset bit
PV not
reset
Not resetReset Reset Reset Reset
One cycle
Reset Bit
Reset Not reset Not reset Not reset
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