Omron CJ2M-CPU Series - Page 152

7 High-speed Counters
7-42
CJ2M CPU Unit Pulse I/O Module User’s Manual
High-speed
Counter 0 Gate Bit
A531.08 If one of these flags is turned ON,
the high-speed counter will not
count even if pulse inputs are
received and the counter PV will be
maintained at its current value.
When the flag is turned OFF, the
high-speed counter will resume
counting and the counter PV will be
refreshed.
This flag will be disabled if the high-
speed counter's reset method is set
to Phase-Z signal + Software reset
and the Reset Bit (A531.00 to
A531.03) is ON.
Read/Write • Cleared when power is
turned ON.
High-speed
Counter 1 Gate Bit
A531.09
High-speed
Counter 2 Gate Bit
A531.10
High-speed
Counter 3 Gate Bit
A531.11
Name Word/Bit Function Read/Write Refresh timing