6-50
TECHNICAL DATA ORBAN MODEL 8685
62250.000.02
N/C
N/C
N/C
N/C
SERIAL PORT ONE
(rear panel)
SERIAL PORT TWO
(rear panel)
D1 & D2
Dual Footprints
- No-stuff -
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
12 @ 0 Ω
No-stuff
From Base Board
SERIAL PORT THREE
(rear panel)
R6
10.0K
R7
10.0K
+5VD
1
2
C18
0.1uF
Tout A
Vcc
Gnd
Tout DTin D
Tin C Tout C
Tin B Tout B
Tin A
Rout A
Rin C
Rout C
Rin B
Rout B
Rin A
V-V+
C2-
C2+C1+
C1-
(TTL)
Rout D
Rin D
(RS232)
6
4
22
17
11
10
12
2
1
24
20
7
3
23
16
15
13
14
8
9
5
18
19
21
MAX208ECNG
U1
12
C6
0.1uF
12
C11
0.1uF
12
C15
0.1uF
12
C12
0.1uF
12
C10
0.1uF
12
C4
0.1uF
12
C1
0.1uF
12
C3
0.1uF
DGND
DGND
+5VD
DGND
DGND
12
C13
0.1uF
DGND
12
C5
0.1uF
A0
A1
A2
/IOR
/IOW
INTD
TXA
/DTRA
/RTSA
RXA
/DSRA
/CTSA
/CDA
/RIA
TXB
/DTRB
/RTSB
RXB
/DSRB
/CTSB
/CDB
/RIB
TXC
/DTRC
/RTSC
RXC
/DSRC
/CTSC
/CDC
/RIC
TXD
/DTRD
/RTSD
RXD
/DSRD
/CTSD
/CDD
/RID
X1 X2
VCCVCC
INTA
INTC
INTB
RESET
SEL16/68
INTSEL
/CSD
/CSA
/CSB
/CSC
/RXRDY
/TXRDY
D0
D1
D2
D3
D4
D5
D6
D7
GND GNDGND
VCC
66
67
68
1
2
3
4
5
34
33
32
52
18
16
20
50
54
37
15
21
49
55
38
39
31
65
30
17
12
14
7
10
11
9
8
19
24
22
29
26
25
27
28
64
35 36 6 23 40 57
47
51
46
48
41
44
45
43
42
53
58
56
63
60
59
61
62
13
ST16C554DCJ68
U4
SOCKET
24-PIN
DIP
SU1
SOCKET
24-PIN
DIP
SU2
1
2
C17
0.1uF
1
2
C20
0.1uF
1
2
C19
0.1uF
+5VD
Tout A
Vcc
Gnd
Tout DTin D
Tin C Tout C
Tin B Tout B
Tin A
Rout A
Rin C
Rout C
Rin B
Rout B
Rin A
V-V+
C2-
C2+C1+
C1-
(TTL)
Rout D
Rin D
(RS232)
6
4
22
17
11
10
12
2
1
24
20
7
3
23
16
15
13
14
8
9
5
18
19
21
MAX208ECNG
U3
12
C14
0.1uF
12
C8
0.1uF
12
C2
0.1uF
12
C7
0.1uF
DGND
DGND
12
C9
0.1uF
SOCKET
24-PIN
DIP
SU3
DGND
+5VD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
J4
1
2
3
4
5
6
7
8
9
Chas
Chas
J1
1
2
3
4
5
6
7
8
9
Chas
Chas
J3
AUX_D7
AUX_D6
AUX_D5
AUX_D4
AUX_D3
AUX_D2
AUX_D1
AUX_D0
AUX_D7
AUX_D6
AUX_D5
AUX_D4
AUX_D3
AUX_D2
AUX_D1
AUX_D0
DGND
+5VD
+5VD
1
2
10uF
C21
1
2
0.1uF
C22
SA2
SA1
SA0
SA0
SA1
SA2
DGND
R5
110 Ω
DGND
R19
R18
R17
R16
R15
R14
R13
R12
R11
R10
R9
R8
ECO# DATE DESCRIPTION DONE CHECKEDREV
Revision History:
3124 WRS
Created for 8500 project.12/15/03 01
---
DGND
R4
100K
R3
100K
R2
100K
R1
100K
+5VD
DGND
1 A.
D1
1 A.
D2
21
3.9uH
L1
Tout A
Vcc
Gnd
Tout DTin D
Tin C Tout C
Tin B Tout B
Tin A
Rout A
Rin C
Rout C
Rin B
Rout B
Rin A
V-V+
C2-
C2+C1+
C1-
(TTL)
Rout D
Rin D
(RS232)
6
4
22
17
11
10
12
2
1
24
20
7
3
23
16
15
13
14
8
9
5
18
19
21
MAX208ECNG
U2
+5VD
DGND
DGND
+5VD
1
2
3
4
5
6
7
8
9
Chas
Chas
J2
CHASSIS
(BRIDGED)
(BRIDGED)
(BRIDGED)
R20
249 Ω
023179 WRSChanged sockets; bridged R11, 15, 19; C16 becomes R20.11/02/04
/CTS3
/CTS3
/DSR2
/DSR2
/DSR3
/DSR3
/DCD2
/DCD2
/DCD3
/DCD3
SOUT3
SOUT3
SIN3
SIN3
/RTS3
/RTS3
/DTR2
/DTR2
/DTR3
/DTR3
/GPIORD
/GPIORD
/GPIOWR
/GPIOWR
SOUTP1
SOUTP1
SOUTP2
SOUTP2
SOUTP3
SOUTP3
RTSP1
RTSP1
RTSP2
RTSP2
RTSP3
RTSP3
DTRP1
DTRP1
DTRP2
DTRP2
DTRP3
DTRP3
SINP1
SINP1
SINP2
SINP2
SINP3
SINP3
CTSP1
CTSP1
CTSP2
CTSP2
CTSP3
CTSP3
DSRP1
DSRP1
DSRP2
DSRP2
DSRP3
DSRP3
DCDP1
DCDP1
DCDP2
DCDP2
DCDP3
DCDP3
/CTS2
/CTS2
/RTS2
/RTS2
SIN2
SIN2
SOUT2
SOUT2
/DCD1
/DCD1
/DSR1
/DSR1
/CTS1
/CTS1
/DTR1
/DTR1
/RTS1
/RTS1
SIN1
SIN1
SOUT1
SOUT1
RSTDRV
RSTDRV
PATCH2
/AUX_0
/AUX_0
/AUX_1
/AUX_1
/AUX_2
/AUX_2
/AUX_3
/AUX_3
18.432MHz
18.432MHz
PATCH1
PATCH3
PATCH4
RIGnd
RIGnd
RIGnd
RS232 Board Schematic Drawing
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