Circuit Descriptions, Abbreviation List, and IC Data Sheets
EN 178 Q528.1A LA9.
9.7.4 Control and Compute Subsystem
Refer to figure “Control and compute subsystem” for a
clarification of the blocks that are used in this device.
Figure 9-16 Control and compute subsystem
The Control and compute subsystem consists of the main
processor, control peripherals and the memory system.
The MIPS 4KEc is a 32-bit MIPS RISC core. It has direct
access to connectivity peripherals to support system features
via PCI, I
2
C, UART or General Purpose I/O. A JTAG interface
provides processor software debug capabilities.
The Memory Control Unit (MCU) is a 32-bit DDR2 SDRAM
interface supporting DDR2-533 with an address range of 128
MB (max.).
The PCI/XIO interface supports PCI Rev2.2 and can be used
to access 8/16-bit external NAND-Flash memory.
The Conditional Access Interface supports direct control and
communication to the PC-Card attached to a PCMCIA
interface. The interface supports the DVB CI-CA and
CableCard specification.
9.8 Back-end
Refer to figures “Architecture of TV520 platform” earlier in this
chapter for details. Refer also to block diagrams B04, B05, B06
and AB.
Table 9-1 Back-End key component overview
H_16770_126.eps
130707
D
C
S
-
N
e
t
w
o
r
k
I2C-3
MCU
D
M
A
B
u
s
PNX85xx
DDR2-SDRAM
I2C-DMA3
I2C-2 I2C-DMA2
PCI/XIO
PCI/XIO
2-wire UART1
2-wire UART2
MIPS
MTI-4KeC
System
Controller
80C51
I2C-4
UART-3
PWM’s
GPIO’s
CAI
CA
I2C-1 I2C-Slave
E-JTAG
E-JTAG
DMA
Region/
specification Processing
Picture
enhancement DFI panel
HD @ 50 Hz PNX5050 Pacific 3 no
HD @ 100 Hz
fHD @ 50 Hz
fHD @ 100 Hz yes
To Next Page