Circuit Descriptions, Abbreviation List, and IC Data Sheets
EN 182 Q528.1A LA9.
9.8.6 PACIFIC 3 (T6TF4HFG)
The PACIFIC 3 performs the following tasks:
• Colour processing.
• Sharpness improvement.
• Backlight dimming.
• AmbiLight.
• Display (LVDS) switch on/off.
• Pattern generator.
The PACIFIC 3 interfaces:
• Video input:
– EU sets: CMOS from PNX5050
• Video output: LVDS (single or dual) to display or DFI panel.
• Backlight dimming: pulse-width modulated (PWM) followed
by PWM to I
2
C conversion.
• AmbiLight: pulse-width modulated (PWM) followed by
microprocessor.
Refer to figure “PACIFIC 3 CMOS + LVDS interface” for details.
Figure 9-23 PACIFIC 3 CMOS + LVDS interface
A configuration flash memory is added (item 7GE1).
Figure 9-24 PACIFIC 3 control (diagram B06C)
Single LVDS
-
in
(
PNX85xx )
Double LVDS in
(
FPGA
)
Single or double
LVDS
-out to display
PW M ambi
to µP
H_16770_137a.eps
240707
CM OS i nput
From
PNX5050
:Vsync
LCD -Power -ON
I2C SSB
RESET from PNX85xx
Vsync to Scanning
Back Light D isplay
Resonator 60MHz
To dimming circuit
Configuration
Flash memory
H_16770_138.eps
130707
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