Philips 32PFL9432/98 - 9.8.3 Full-HD sets @ 100 Hz - Dynamic Frame Insertion; 9.8.4 PNX85 xx

Circuit Descriptions, Abbreviation List, and IC Data Sheets
EN 180 Q528.1A LA9.
9.8.3 Full-HD sets @ 100 Hz - Dynamic Frame Insertion
All full-HD sets with a refresh rate of 100 Hz have an additional
panel for upscaling the outcoming signal from the Pacific 3 to
100 Hz @ 1080p. Refer to figure “Block diagram display control
Full-HD sets 100 Hz with DFI panel” and diagram AB for
details.
Figure 9-19 Block diagram display control Full-HD sets 100 Hz with DFI panel
9.8.4 PNX85xx
For sets where the PNX85xx outputs LVDS to the PACIFIC 3,
refer to figure “PNX85xx LVDS interface to PACIFIC 3” for
details.
Figure 9-20 PNX85xx LVDS interface to PACIFIC 3 (diagram B04O)
For sets where the PNX85xx outputs CMOS to the PNX5050
or CYCLONE II (EP2C8F256C7N), refer to figure “PNX85xx
CMOS interface to PNX5050 or CYCLONE II” for details.
DFI2k7
LVDS 51p - FI-R51S-HF
AmbiLight
MUX
+
Level
shift
1M59
I2C-Ambi
DC / DC
+1V2
+3V3
I2C4
LVDS
4x LVDS
2x LVDS
41p
1F00
JTAG
Flash
DDR
6 pin
27Mhz
LVDS 41p - FI-R41S-HF
DDR
MOP2K7-
AMBI
Flash
75Mhz
+2V5
+12V
Switch
+12V
LVDS 41p - FI-R41S-HF
LVDS 51p
1F02
JTAG
Spread
Spectrum
H_16801_016.eps
240707
H_16770_131.eps
240707
7H00-7
PNX85xx