R8C/20 Group, R8C/21 Group 12. Interrupts
Rev.2.00 Aug 27, 2008 Page 97 of 458
REJ09B0250-0200
12.1.6.5 Interrupt Response Time
Figure 12.7 shows an Interrupt Response Time. The interrupt response time is the period between an interrupt
request generation and the execution of the first instruction in an interrupt routine. An interrupt response time
includes the period between an interrupt request generation and the completed execution of an instruction
(refer to (a) in Figure 12.7) and the period required to perform an interrupt sequence (20 cycles, refer to (b) in
Figure 12.7).
Figure 12.7 Interrupt Response Time
12.1.6.6 IPL Change when Interrupt Request is Acknowledged
When an interrupt request of a maskable interrupt is acknowledged, the interrupt priority level of the
acknowledged interrupt is set in the IPL.
When a software interrupt and special interrupt request are acknowledged, the level listed in Table 12.5 is set to
the IPL.
Table 12.5 lists the IPL Value When Software or Special Interrupt Is Acknowledged.
Table 12.5 IPL Value When Software or Special Interrupt Is Acknowledged
Interrupt Sources Value Set to IPL
Watchdog Timer, Oscillation Stop Detection, Voltage Monitor 2, Address Break 7
Software, Address Match, Single-Step Not changed
Interrupt request is generated Interrupt request is acknowledged
Instruction Interrupt sequence
Instruction in
interrupt routine
Time
(a) 20 Cycles (b)
Interrupt response time
(a) Period between an interrupt request generation and the completed execution of an
instruction. The length of this time varies depending on the instruction being executed.
The DIVX instruction requires the longest time; 30 cycles (no wait and when the register
is set as the divisor)
(b) 21 cycles for address match and single-step interrupts.
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