Sanyo PLC-XP200L - Input & Signal Processing Stage

-66-
Chassis Description
DVI-D
PJ-Net
INPUT1
D_SUB15D_SUB15
INPUT2
BNC
13 11
1,3,5
8,10,12
1,3,5
13,3 12.5
5 6 2 7
15,17
RCAS-VIDEO
INPUT3MONITOR
OUT
SCART_R
OUT_R/CR
OUT_G/Y
OUT_B/CB
OUT_HS
OUT_VS
OUT_SW
SCART_G
SCART_B
S-C
Y_IN_PW
CB_IN_PW CR_IN_PW
S-Y
SCART_CV
S-C_PW
S-Y_PW
VIDEO
SCART_CV_PW
INPUT2_VS_EX
INPUT2_HS_EX
INPUT2_VS
INPUT2_HS
INPUT2_VS
INPUT2_HS
-IN1/IN2
Q251
IC2001
BNC/RCA-SW
<AD8183>
IC5001
IN1/IN2-SW
<AD8183>
IC1002
SYNC-SW
<TC4053>
IC4001
BUFFER-SW
<AD8075>
IC4002
BUFFER-SW
RGB
HV HV
RGB
Y,CR,CB
AV
MAIN
K21A K10A
RGB
Q4001
HV
IC301
<PW392>
SYSTEM
CONTROL
&
SCAN
CONVERTER
8,10,12
10,12,14
3,6
IC1011
SYNC
SEP.
<BA7078>
IN2:H
-BNC/RCA
RCA:H
OUT:H
-IN1/IN2
IN1:H
171 204 131
122
20
22
-IN1/IN2
Y:H
5
1
3
22
7 5 3
1 1
7
5 2
9,11
14 20 18 16 4
18 16
14 12 10
123
27 31
133 240 338 313
105 109 210 311 209 138 318 104 206 307
243
67
118
25
5 3 7
IN0_HS
IN0_VS
IN0_CLK
CG_HSYNC
CG_VSYNC
120
8
CG_CLK
IC5201
PC/PJ-NET SW
FPGA
<>
IC2201
PC A/D
<ISL510002>
IC8001
DVI
EQUALIZER
<>
IN0B[0-9] IN0G[0-9] IN0R[0-9]
CG_B[0-9] CG_G[0-9] CG_R[0-9]
PC_R
PC_G
PC_B
R_IN
G_IN
B_IN
49
VSOUT
HV_SW
50
HSOUTHS
VS
OUT_HS
OUT_VS
7 3
5 2
IC261
3 7
2 5
IC262 IC211
14 12 10
5 3 7
IC221
14 12 10
5 3 7
IC231
Y_IN
CB_IN CR_IN
Y_IN
CB_IN CR_IN
SCART_CV
IC1006
57
111
|
118
53 47 62 61 37 33 29 21 17 25 45 41
Q1341,Q1342, Q1342,
Q1344, Q1345
AMP
Input & signal processing stage