2.11 Undervoltage and Overvoltage Protection (optional)
155
7SD610 Manual
C53000-G1176-C145-4
Figure 2-56 Logic diagram of the overvoltage protection for the negative sequence voltage system U
2
The overvoltage protection for the negative sequence system can also be blocked via
a binary input „>U2>(>) BLK“. The stages of the negative sequence voltage protec-
tion are automatically blocked as soon as an asymmetrical voltage failure was detect-
ed („Fuse–Failure–Monitor“, also see Section 2.15.1, margin heading „Fuse Failure
Monitor (Non-symmetrical Voltages))“ or when the trip of the mcb for voltage trans-
formers has been signalled via the binary input „>FAIL:Feeder VT“ (internal indi-
cation „internal blocking“).
During single-pole dead time the stages of the negative sequence overvoltage protec-
tion are automatically blocked since arising negative sequence values are only influ-
enced by the asymmetrical power flow, not by the fault in the system. If the device co-
operates with an external automatic reclosure function, or if a single-pole tripping can
be triggered by a different protection system (working in parallel), the overvoltage pro-
tection for the negative sequence system must be blocked via a binary input during
single-pole tripping.
Overvoltage zero
sequence system
3U
0
Figure 2-57 depicts the logic diagram of the zero sequence voltage stage. The funda-
mental frequency is numerically filtered from the measuring voltage so that the har-
monics or transient voltage peaks remain largely harmless.
The triple zero sequence voltage 3·U
0
is fed to the two threshold stages 3U0> and
3U0>>. Combined with the associated time delays T 3U0> and T 3U0>> these stages
form a two-stage overvoltage protection for the zero sequence system. Here too, the
drop-off to pickup ratio can be set (3U0>(>) RESET). Furthermore, a restraint delay
can be configured which is implemented by repeated measuring (approx. 3 periods).
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