Sony HAP-S1 - Block Diagram - DIGITAL AUDIO INPUT Section

HAP-S1
HAP-S1
4141
5-2. BLOCK DIAGRAM - DIGITAL AUDIO INPUT Section -
J4023
COAXIAL IN
WAVE
SHAPER
IC4002
OPTICAL IN
OPTICAL
RECEIVER
IC4001
DIGITAL AUDIO INTERFACE RECEIVER
IC4004
RXIN163
D/A CONVERTER
IC405
DATA5
BCK6
LRCK4
FPGA
IC001 (2/2)
IO/DIFFIO_R2N
D12
SCL7
RXIN6
XOUT
XIN
58
DATAOUT
16
BCKOUT
14
LRCKOUT
15
XMCK 30
MCKOUT 13
DIR_MISO
SO
27
39
SI
38
SCK
37
DIR_CE
CSB
30
36
DIR_INT
INTB
19
DIR_MOSI
28
DIR_SCK
29
40
DIR_NLPCM
NPCMF
20
25
XMODE
35
ERRF
23
DIR_CKST
MUTEB
32
24
DIR_ST_DATA
18
DIR_SEL
16
DIR_RESET
36
DIR_ERROR
31
FREQUENCY MULTIPLIER
IC4008
LOCK#
CLK_IN
5 CLK_OUT 3
4
CLOCK SELECTOR
IC4006
SELECT
A
B
1
2
Y
5
6
CLOCK SELECTOR
IC410
SELECT
A
B
1
2
Y
5
6
CLOCK SELECTOR
IC407
SELECT
B
A
2
1
Y
5
6
DATA/CLOCK SELECTOR
IC4007
SELECT
A3
DATA_DSDL
A2
14
B3
13
B210
11
A1D4003
B16
5
Y3
Y2
Y1
12
IOUTL+
25
IOUTL–
26
IOUTR+
17
IOUTR–
18
9
7
A0
B03
2
Y0
4
1
31
32
X4001
24.576MHz
SWITCHING
IC412
CLOCK
BUFFER
IC408
CLOCK
BUFFER
IC409
COUNTER
IC411
LINE AMP
IC402
MIX AMP
IC400
LINE AMP
IC401
MDI 11
IO/DIFFIO_R4P/DM0RE10MC 12
IO/DIFFIO_R2PD11!MS! 10
IO/DIFFIO_R14P/DQ0RK11
IO/DIFFIO_R13N/DQ0R
DATA_DSDL
BCLK-L
L13
IO/RUP3
N13
IO/DIFFIO_R9P/DQ0R
K13
CLK4/DIFFCLK_2N
G13
IO/DIFFIO_R13P/DQ0RL12
IO/DIFFIO_R14N/DQ0R
AMUTE
K12
!RST!
14
BCLK-L
LRCLK_DSDR
LRCLK_DSDR
X400
22.5792MHz
X401
24.576MHz
L L, R
R
>002B
D_ERROR AMUTE, D_ERROR, D_CKST
D_CKST
>003B
SYSTEM CONTROLLER
IC5006 (2/5)
: AUDIO (DIGITAL)
: AUDIO IN (DIGITAL)
SIGNAL PATH
: AUDIO (ANALOG)
(Page 42)
(Page 42)