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PROGRAMMING AND INTERFACING
Save Setup – Sn – where n=1-9
Recall Setup – Cn – where n=0-9
Limits – L0, L1, L2, L3, L4
Status – U0, U1, U2, U3, U4, U5, U6, U7
Serial Polling
Mnn – where “nn” is the decimal equivalent mask value.
Setting the SRQ Mask Bits allow the 1750 to signal the controller when a significant event occurs. The
decimal values that are allowable for the Mask range from 0-63. This decimal value is converted to a
binary masking byte, which is “AND”ed with the 1750 status byte. The resulting byte indicates whether
an SRQ will be generated by the 1750. A true status is indicated by a binary 1 in the status byte. The
assignment of bits for the 1750-status byte are as follows:
1750 Status (Control) Byte
Examples of mask settings and their respective results.
“M63” will allow SRQ’s for all of the 1750 status bits. Since a binary 63 is represented by 11111111,
this value is “AND”ed with the status byte allowing all states to transfer to the controller to generate
and SRQ.
“M32” will allow SRQ’s on Error States Only. This is bit #5. Since bit #5 is the only allowable bit allowed
by the mask ONLY error states will generate an SRQ condition.
The error bit is the only status bit that is latched when it becomes true. All of the other status bits will
be cleared after being read by the serial poll of the bus. The Error Bit will remain latched until a U1X
command is sent to the 1750 and a status is returned to the controller.
After an SRQ is generated on the bus, serial polling the bus returns the serial poll byte. If the Model
1750 is the device generating the SRQ, the #6 bit, (64 binary value), is set in the serial poll byte along
with the applicable status bits. The returned value will yield the value of the #6 bit, (64), plus the
decimal value of the active status bits.
BIT7 BIT0BIT1
BIT3 BIT2BIT4BIT5
BIT6
SELF TEST
COMPLETE
READY
FOR INPUT
ERROR
RSV
NOT
USED
NOT
USED
NOT
USED
READING
DONE
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