Circuit Descriptions
5–14
1502C MTDR Service Manual
The combined video and position signal is amplified by the user-selected gain in the
video amplifier. Gain of the amplifier is set by the processor system via the data bus
and video amplifier select signal.
The amplified video is digitized by the video ADC upon receipt of a control signal
from the processor system. The processor is notified by the ADC interrupt request
when the conversion has been completed. The processor then reads the value via the
data bus.
The vertical position DC voltage is generated by a digital-to-analog converter
consisting if U2046 and U3041. DAC integrated circuit U2046 receives a +2.5 VDC
reference voltage from U3040 and multiplies it by a 14-bit digital value loaded from
the data bus under control of the processor. The resulting current output of U2046
is amplified by operational amplifier U3041 to a proportional voltage of zero to
–2.5 VDC.
The summing amplifier consists of operational amplifier U8041; input resistors
R8044, R8046, and R8047; and a feedback resistor, R8045. Summation of the DAC
output through R8047 with the +2.5 VDC reference through R8046 causes the
vertical position signal range to be enlarged and shifted to achieve an effective
output of –2.5 VDC to +2.5 VDC.
Sampled video, through R8044, is summed with the vertical position signal at the
input node of U8041. Resistor T8045 determines the gain of U8041 and is paralleled
with C8040 to reduce high frequency gain for noise reduction. The sampled video
input may be observed at TP9041.
Combined video from the summing amplifier is further amplified by a three-stage
programmable video amplifier.
The first stage of this amplifier consists of amplifier U7040, voltage divider T8040
through R8043, and analog multiplexer U8040. Voltage gains of 0, 16, 32, or 48 dB
are achieved by switching U8040 to connect one of the four points from the resistive
voltage divider to the inverting input of U7040. This causes the amplifier gain to
be equal to the attenuation factor of the voltage divider point selected.
The second stage consists of amplifier U5040, voltage divider R6040 through
R6047, and analog multiplexer U6040. This stage operates similar to the first stage
except eight voltage gains are provided from 0 to 14 dB in 2-dB steps.
The third stage consists of amplifier U3042, voltage divider T4040 through R4047,
and analog multiplexer U4040. This stage operates similar to the first and second
stages except eight voltage gains are provided from 0 to 1.75 dB in 0.25-dB steps.
Gain of each of the three amplifier stages is controlled by the processor system by
loading latch U2044 with the appropriate 8-bit word from the data bus. Digital word
Vertical Position DAC
Summing Amplifier
Video Amplifier
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