Theory of Operation—2230 Service
pin 1 of U3112A, and NAND-gate U3112 is disabled from
passing the selected clock signal. U3112A puts a HI on
pin 13 of U3112D, enabling U3112D to pass the divided
clock signal to the D input of flip-flop U3102A. Rising
edges of ADCLK transfer the inverted state of the signal
at the D input of U3102A to the CHAN1 signal line, switch
ing the Analog-Channel Switch at one-half the SAVECLK
frequency. In Sampling and XY Sampling Modes,
MIN/MAX is LO. This disables U3313D, stopping the
divided clock, and enables U3112 to pass the selected
clock to the D input of U3102A. Then, the selected clock
and CHANl are the same frequency. Another 50 ns of
delay is added when clocking through U3102A. The delay
is present for either selected clock.
MEMORY CONTROL. Memory Control multiplexer
U3417 selects the enabling and read-write signals that
control the Acquisition Memory. When the ACQWRITE
clock goes HI (see Figure 3-9), the multiplexer turns the
memory over to the Acquisition System (1 inputs) to per
forms write to memory. From the inverting multiplexer,
the E enabling signal (pin 7) is a fixed LO that selects the
Acquisition Memory devices for access. The G enabling
signal (pin 4) is a fixed HI that disables the memory
devices for outputting data. Writing to memory is con
trolled by the WRITECLK signal_from the Clock Generator
(Diagram 18). It becomes the W (write enable) on pin 9
and the ADDRCLK (memory address clock) on pin 12 of
multiplexer (U3417). When the ACQWRITE signal switches
the multiplexer, one-half a CONV clock period later, the
Swap Registers are enabled onto the memory buses,
transferring from the MIN/MAX Registers the samples that
are to be stored. In another one-half CONV clock period,
the data bytes have settled, and the memories are enabled
for an acquisition write by the LO state of the second half
period of WRITECLK. The WRITECLK falling transition
increments the Address Counters to the address of the
next location to be written to in memory.
For a memory read or memory write by the Micro
processor, the Memory Control multiplexer is switched to
the 1 input signals. RD and WR (read and write control
signals) from the Microprocessor control bus, determine if
a read or write is to be done. Loading the Address
Counter (U3423, U3424, and U3425), enabling the
Microprocessor Data Transceivers (U3421 and U3422),
and gating the control logic is done by the ACQSEL signal.
The signal is the OR of the IO-SEG and BLCK2 signals in
the processor section. Both address selection signals must
be LO to access the Acquisition Memory from the
Microprocessor. The ADDRCLK signal from pin 12 of the
multiplexer is a fixed HI that disables the Address
Counters from counting while the Microprocessor is either
reading from or writing to memory. The RD signal is
inverted to pin 2 of the multiplexer by U3416A, and is
again inverted to pin 4 by the multiplexer. When the
memory is enabled for reading stored data, pin 4 is LO
(RD). The ASQSEL signal is inverted by U3416B and
applied to pin 5 of the multiplexer. It is again inverted
through the multiplexer to a LO, enabling the memory out
puts onto the memory data buses. The WR signal is also
HI to enable the memory for a read.
The Microprocessor writes to the memory only for diag
nostics. WR and ACQSEL must both be LO at the inputs
of U3420C to cause pin 9 of the multiplexer to be LO, ena
bling a memory write. The Address Counters are enabled
for a parallel load of the selected memory address. Only
one memory device at a time is read from or written to by
the Microprocessor, because the microprocessor data
transceivers that buffer data to and from the memory
devices are never both enabled at the same time. The ena
bling signals are gated by U3420A (ODDEN) and U3420D
and U3426A (EVENEN). Address bit AO selects the data
transceiver. When AO is HI, transceiver (U3422) is enabled;
when LO, transceiver (U3421) is enabled. The RD signal
from the microprocessor control bus selects the direction
of transfer through the transceivers. When it is LO, the
transfer is from the memory bus to the microprocessor
data bus (read); when HI, the transfer is from the
microprocessor data bus to the memory bus (write).
Acquisition Memory and Microprocessor Access
The Acquisition Memory stores the acquired waveform
data that will be read out for the stored waveform display, i
In the normal operation, the Acquisition System controls
writing the acquired data bytes, and the Microprocessor
controls reading the data out for display. For diagnostic
purposes, the Microprocessor also has a limited ability to
write to the memory.
The Acquisition Memory is composed of two, 2K by 8-
bit static random-access memories (U3418 and U3419) for
a total of 4K bytes of memory. The memory space is
divided into Odd and Even halves. Single channel data is
stored as odd and even data byte pairs. Dual-channel
operation requires that the Channel 1 data and Channel 2
data be stored in the opposite memory halves for a record
length of 2k bytes each channel. In Min-Max mode, the
minimum and maximum data points of each data pair are
stored in opposite halves of the memory. When both chan
nels are being acquired (CHOP) in Min-Max mode, min
data points and max data points for each channel are
alternately stored in opposite halves of the memory.
Both memories are enabled at the same time for either
reading or writing in parallel. When reading from or writing
to the memories from the Microprocessor, the micropro
cessor data transceivers (U3421 and U3422) are enabled
on opposite states of AO, the least-significant address bit,
to select the half of memory placed on the data bus for
3-36
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