Tektronix 2230 Service Manual

Theory of Operation—2230 Service
Resistor R4213 and C4202 adjust the counter’s gain
and offset. Nominal counts are 300 for maximum and 100
for minimum. The difference of the two counts represents
the 50 ns CONV clock period.
B-Delay Timer
The B-Delay Timer determines the starting address of
the B Display in memory. The length of the record is deter
mined by the setting of the SEC/DIV switch and the
acquisition-mode information (i.e. is it CHOP, single trace,
or a IK or a 4K acquisition). The BTRIGD signal (U4121A
pin 5) goes HI on the first falling edge of RECCLK after
the B-GATE signal goes HI. BTRIGD going HI causes
U4123 and U4124 to latch the value of the Record
Counter. The microprocessor then reads the starting
address from U4123 and U4124, which are enabled by
10 2,10 1, and A5 (Address Decode).
DIGITAL DISPLAY
A custom LSI integrated circuit controls the stored
waveform and readout displays. Six 16K x 4-bit random-
access memories (RAM) make up the Display Memory.
Four of the RAM chips provide 32K x 8-bit waveform data,
and two RAMs hold the 32K x 4-bit waveform-attribute
data. Waveform data may be stored in the RAM from data
on the Microprocessor bus or data may be read from the
RAM and transferred to a Communication Option. For
waveform displays, data is read from the RAM (display
memory) by the display controller. The display controller
then processes the data, and then drives the Vertical (Y)
and Horizontal (X) digital-to-analog converters (DAC)
where the data is converted to analog voltages used to
drive the X- and Y-Axis vector generators.
Data Transceivers
Communication between the Microprocessor and the
display memory is via two bus transceivers, U9206 and
U9207. Waveform data from the Acquisition Memory is
transferred to the display memory where the data is
always available to the Display Controller for refreshing
the display. The data transceivers are enabled by logic
gating in U9211 that decodes the PA15 and PA14 signals
from the Microprocessor and the PROCEN signal from the
Display Controller to determine when a transfer is possi
ble. The direction of transfer is controlled by the WR
(write) signal from the Microprocessor. The WR signal also
enables U9211 to allow either a read from memory (for
outputting data) or a write to memory (for transferring in
the data from the Acquisition Memory). Bus transceiver
U9206 is enabled for 8-bit data transfers and transceiver
U9207 is enabled for 4-bit transfers.
Address Decoder
To access a byte in RAM, a row address followed by a
column address is required. Row and column memory
addresses are written together as one address word from
the Microprocessor. Address Decoders U9204 and U9205
are switched by the ROW/COL signal from the Display
Controller to select either the row address or the column
address from the Microprocessor address bus. The RAS
and CAS signals enable the address latches, internal to
each display RAM, to latch the selected row and column
addresses. Column addresses are decoded from the mid
dle six bits of the 8-bit address by address decoders in
each RAM. Row addresses require all eight bits. The
Display Controller has direct access to addresses in the
RAM using the RA bus.
RAM
Six 16K by 4-bit memories make up the display RAM.
The 8-bit waveform bytes are stored with the lower four
bits in U9203 and U9233 and the higher four bits in U9202
and U9232. The remaining RAMs (U9201 and U9231)
store attribute bits that are used to define the waveform
print intensity and mark the end of the record. The
memories are arranged in a 256 X 64 row and column for
mat to allow eight addressing lines to access the 16K of
4-bit memory addresses (64K-bits of memory).
Memory refreshing is satisfied whenever the 256 Row i
addresses are accessed. Refreshing occurs when the
Display Controller does a memory read for display pur
poses. While the Microprocessor is controlling the Display
Memory, it must also perform memory refreshing by
activating all the memory Row addresses. To maintain the
dynamic memory, a refresh must be done at least every
eight milliseconds.
DATA TYPES. The data stored in the Display Memory
is either readout characters or waveforms. The micropro
cessor also uses the display memory for operational data
storage. In either case a 9-byte field-attribute preamble is
read first. The preamble defines the data type and sets up
the display attributes. Readout information is displayed
using short vector X-Y displays positioned to specified
fields on the crt.
Display C ontroller
The Display Controller runs the display system for the
STORE waveform and STORE and NON STORE readout
displays. It takes control of the RAM to read the waveform
or readout data. Besides the waveform data, the Display
Controller runs the Store Z-Axis, selects the type of
display (vector, dots, or X-Y plotter output), and drives the
horizontal and vertical channel switches.
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Tektronix 2230 Specifications

General

Brand	Tektronix
Model	2230
Category	Test Equipment
Language	English