Theory of Operation—2230 Service
ADD DISPLAY. In the ADD position of S545, both the
Set and Reset inputs_of U540A are held LO by CR534 and
CR537. The Q and Q outputs of U540A are then both HI,
and signal currents from the Channel 1 and Channel 2
Preamplifiers add together to drive the Delay Line Driver.
CHOP DISPLAY. In the CHOP position, the
CHOP ENABLE line is held LO, keeping the Q output of
flip-flop U540B HI. This enables CHOP multivibrator
U537D to begin switching. The switching rate is deter
mined primarily by the component values of R544, R545,
and C545. The output of U537C (the inverted output of the
multivibrator circuit) drives U537A and supplies the CHOP
clock to flip-flop U540A. The output of U537C also drives
U537B, the CHOP Blanking Pulse Generator (see
Diagram 9).
Coupling capacitor C547 and resistors R547 and R548
on pin 5 of U537B (see Diagram 9) form a differentiating
circuit that produces short duration pulses during the
switching of U540A. These pulses are inverted by U537B
to generate the Chop Blank signal to the Z-Axis Amplifier.
The pulses blank the crt during CHOP switching times.
The Alt Sync signal on pin 2 of U537A (see Diagram 2)
is HI except during hold off. While pin 2 is HI, the output of
U537C is inverted and passed by U537A to the clock input
(pin 3) of U540A. Since the '5' output of U540A is con
nected back to the D input, and both the Set and Reset
inputs are HI, the outputs of U540A switch (change states)
with each clock input. The Delay Line Driver is then sup
plied alternately from the Channel 1 and Channel 2
Preamplifiers at the CHOP rate.
ALTERNATE DISPLAY. In ALT, the CHOP ENABLE
line is held HI, disabling CHOP multivibrator U537D. The
output of U537C, the chop blanking signal, is HI. Input sig
nals to U537A are the HI from U537C and ALT SYNC
from the Hold-Off circuitry in the A Sweep Generator. The
output of U537A is then the inverted ALT SYNC signal
that clocks Channel Select flip-flop U540A. The
ALT SYNC clock toggles the outputs of U540A at the end
of each sweep so that the Channel 1 and Channel 2
Preamplifiers alternately drive the Delay Line Driver.
STORE MODE DISPLAYS. Under direction from the
Display Controller, multiplexer U7201 selects either non
store or store signals to drive the Delay Line Driver. In
NON STORE, the multiplexer switches the Q and Q out
puts of U540A to the Channel Switch to allow the switch
ing sequences just described. However, when STORE is
selected, the nonstore analog signal to the Channel Switch
is turned off, and the store vertical deflection analog sig
nals are applied to the Delay Line Driver input. The store
waveform display is determined by the Display Controller.
The nonstore output transistors are biased off by set
ting pins 9 and 12 of U7201 LO. The forward bias is
removed, and the nonstore path is disabled. Pin 7 of
U7201 is switched LO in STORE mode. Inverter U7202B
inverts the LO, supplying forward bias to the store output
transistors in both Preamplifiers. Selection of either chan
nel signal for digitizing is done by a channel switch 1C in
the Storage Acquisition circuit (Diagram 10).
The HI STORE ENABLE signal from U7202B also goes
to the Sweep Sep circuit to disable that circuit during
STORE mode and to Horizontal Diode Gate circuit
(Diagram 7) to block the nonstore sweep signals from
going to the Horizontal Output Amplifier. To complete the
switching to STORE mode, Pin 4 of U7201 is switched HI
and applied to Inverter U7202B. The LO output signal
from U7202B (STORE) is applied to the Vertical Channel
Switch circuit to pass the STORE mode vertical deflection
signal to the Delay Line Driver. That same LO signal also
goes to the Horizontal Mux to pass the STORE mode hor
izontal deflection signal to the Horizontal Output Amplifier.
A Z-Axis disabling signal DIS Z applied to NAND-gate
U537B (see Diagram 9) disables the Chop Blanking cir
cuitry for STORE mode displays. (DIS Z) holds the output
of the Chop Blanking circuit HI to block the nonstore Z-
axis signals from the Z-Axis Amplifier.
VERTICAL OUTPUT AMPLIFIER
Vertical Output Amplifier circuitry, shown on Diagram 3,
amplifies the vertical signal and drives the crt deflection
plates. The Delay Line Driver converts the signal into a
signal voltage to drive the Delay Line. Delay Line DL9210
delays the vertical signal so that the leading edge of the
triggering signal can be viewed. The BW LIMIT switch
reduces the bandwidth of the Amplifier when required by
the application. The Vertical Output Amplifier drives the
vertical deflection plates of the crt. The A/B Sweep
Separation circuit vertically positions the Nonstore B trace
with respect to the Nonstore A trace in Alt Horizontal
mode displays.
Delay Line Driver
The Delay Line Driver converts the signal current from
the Vertical Preamplifiers or the Store mode Vector Gen
erator circuitry into a signal voltage to drive the Delay
Line. Transistors Q202, Q203, Q206, and Q207 form a
differential shunt feedback amplifier with the gain con
trolled by feedback resistors R216 and R217. Amplifier
compensation is provided by C210 and R210, and output
common-mode dc stabilization is provided by U225.
Should the dc voltage at the junction of R222 and R223 {
move off zero, U225 changes the base current supplied to
3-12
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