Theory of Operation— 2230 Service
Transistors Q770, Q775, and Q779, as one-half of the
complementary differential circuit, form a cascode-
feedback amplifier for driving the right crt horizontal
deflection plate. Amplifier gain is set by R775, with C775
providing high-frequency compensation. For low-speed sig
nals, Q779 serves as a current source for Q775. At high
sweep rates, the deflection signal is coupled through C779
to the emitter of Q779 to provide added pull-up output
current to drive the crt. The amplifier formed by Q780,
Q785, and Q789 drives the left crt horizontal deflection
plate in the same manner as described above, with zener
diode VR782 shifting the collector signal level of Q780 to
the correct level to drive the emitter Q785.
The BEAM FIND function is active when S390 is
pushed in to disconnect the cathode of CR764 from the
— 8.6 V supply. The voltage on the cathode of VR764
goes positive, causing CR780 and CR770 to be forward
biased. Current from R764 causes the output common
mode voltage of the two shunt-feedback amplifiers to be
shifted negative to reduce the available voltage swing at
the crt plates. This stopl the trace from being deflected
off-screen horizontally. The BEAM FIND voltage also goes
to the Vertical Output Amplifier, and the vertical deflection
is limited in that circuit when the voltage is removed.
A circuit formed by Q7501 and Q7502 supplies refer
ence voltages for the 1 K and 4 K storage acquisitions and
for the variable SEC/DIV control, R721. Transistor Q7502
provides a 0.6 V drop from the -8.6 V supply to generate
a —8 V reference for the IK REF and one end of poten
tiometer R721. The 4K REF is produced by Q7501 and is
adjusted by using the RATIO ADJ potentiometer to set the
correct ratio for the two reference voltages. This reference
level also goes to the other end of R721. The wiper volt
age of R721 is the HOR REF voltage for the A and B
Sweep timing resistors in NONSTORE mode. In STORE
mode, either the IK REF or the 4K REF voltage level is
applied to the A and B Sweep timing resistors. Switching
between reference levels for the different modes is done
by the Storage Panel ACQUISITION switches (located on
Diagram 14).
Probe Adjust
The Probe Adjust circuitry, shown on Diagram 7, is a
square-wave generator and diode switching network that
produces a negative-going square-wave signal at PROBE
ADJUST connector J9900. Amplifier U985 forms a multivi
brator that has an oscillation period set by the time con
stant of R987 and C987. When the output of the multivi
brator is at the positive supply voltage, CR988 is forward
biased. This reverse biases CR989, and the PROBE
ADJUST connector signal is held at ground potential by
R990. When the multivibrator output switches states, and
is at the negative supply voltage level, CR988 is reverse
biased. Diode CR989 becomes forward biased, and the cir
cuit output level drops to approximately —0.5 V.
MICROPROCESSOR AND
STORE-PANEL CONTROLS
The Microprocessor, shown on Diagram 14, directs the
operation of the Storage and digital circuitry in the oscillo
scope by following firmware control instructions stored in
the Microprocessor memory. The Store-Panel Controls are
monitored by the Microprocessor to detect when a
Storage operation is selected. The rest of the significant
front-panel controls are monitored through the Front-Panel
A-to-D converter and I/O interface circuitry. Circuit opera
tion is then directed by the Microprocessor to perform the
selected operation.
Microprocessor, Clock, and Timer
Microprocessor U9111 is the center of control activities.
It has an eight-bit combination bidirectional data bus for
information transfer and addressing (ADO through AD7)
and a 12-bit address bus for selecting the source or desti
nation of the data transfers (A8 through A19). Precise tim
ing of instruction execution, addressing, and data transfer
is provided by an external, crystal-controlled oscillator,
shown on Diagram 18 and Clock Generator U9104.
A divide-by-three circuit in Clock Generator U9104
reduces the 20 MHz external input from the crystal oscilla
tor circuit to 6.7 MHz for clocking the Microprocessor. An
output from the 6.7 MHz clocking signal also drives the
Display Controller (U9208 on Diagram 15) to time those
devices. Another clock signal (PCLK) output, at one-half
the Microprocessor clock frequency (3.3 MHz), is supplied
to the input to U9108, a binary ripple counter that pro
duces a lower frequency timing signal. The 6.7 MHz signal
is also included in the Control Bus to provide a clocking
signal for future options.
The RESET output of U9104 provides a power-on reset
signal under normal operation or a manual reset using
jumper connector P9104. The RES voltage level at pin 11
is held below the switching threshold of an internal Schmitt
Trigger circuit after the power is applied for a time period
set by the RC time constant of R9107 and C9107. This
holds the Microprocessor in the reset state until the power
supply voltages are high enough to permit normal opera
tion of the digital circuitry. The Microprocessor is held
reset during the delay period. Manually moving jumper
P9104 to the RESET position forces a reset of the
Microprocessor and the Display Controller.
The only RAM available for general use is the Display
RAM. It’s access is mediated by the Display Controller
and associated circuitry. To allow the Display Controller to
have first priority access to the RAM, the RDY1 input to
the clock generator is used to tell the Microprocessor to
wait for access to the RAM.
3-25
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