If trigger signals are being received, U502 remains set. As
long as U502 is set, the output of U532D is HI, causing
the output of U532C to be LO. Dual flip-flop U506 then
responds to trigger signals at Clock input pin 6 as
described in the "NORM" part of this discussion. If trigger
signals are not being received by U502, its output and the
output of U532D are both LO. With a LO on pin 10 of
U532C, its output is the inverse of the input signal applied
to pin 11. At the end of hold-off, that output goes HI, mak
ing U506 pin 2 LO and pin 3 HI. This automatically gen
erates the A Gate and A Gate signals, generating a
sweep. The Auto Baseline continues holding NOR-gate
U532C enabled so that new sweeps are generated at the
end of hold-off as long as trigger signals are not received
at U502.
Theory of Operation—2230 Service
SGL SWP. The following discussion presumes Nonstore
mode. In Sgl Swp mode, both the P-P AUTO and NORM
front-panel buttons are in their out position. This results in
a LO at the output of U532C that does not permit flip-flop
U506 pin 3 to be held HI. A LO is also on input pin 4 of
U532A.
During hold-off, U532B makes U506 pin 14 HI and
pin 15 LO, causing pin 7 (the D input) of U506 to be HI.
After hold-off ends, clock signals (triggers) to U506 pin 6
keep U506 pin 3 LO, keeping the sweep generator held
off. When the SGL SWP button is pushed in, pin 7 of
U504A goes LO for a time period determined by the time
constant of R504 and C504 and then returns HI. The HI
clocks the HI on input pin 10 of U506 to output pin 15.
Consequently the output of U532A goes LO, and CR514 is
reverse biased to bias Q511 on, lighting the READY LED.
The next trigger pulse applied to input pin 6 of U506 starts
a sweep as described previously. At the end of the sweep,
U506 pin 15 goes LO and pin 14 goes HI, causing the
TRIG’D LED to go out and placing a HI on the input pin 7
of U506. A new sweep cannot be started until the SGL
SWP button is again pressed, resetting the sweep.
In STORE mode, the major difference is that the STO-
RDY line is not true until the processor recognizes that a
trigger has occurred. This prevents the SGL SWP button
from affecting the circuit directly. Instead, the processor
determines the button was depressed, releases STO-RDY,
causing the effect described above when a button is
depressed in Nonstore mode.
X-Y. In the Nonstore X-Y mode, the XY signal is LO
and Q522 is biased on, pulling pin 7 of U532B LO. The
output of U532B holds U506 pin 3 LO and pin 2 HI, and
no sweeps can be started during X-Y mode. Nonstore X-
Axis deflection (horizontal) is determined by the CH 1 OR
X input signal. In STORE mode, the A Sweep Logic circuit
must run to produce the gating required to synchronize the
Storage signal acquisition. The Store signal forward biases
CR7140 to override the XY signal, and the A Sweep Logic
circuitry operates as in Y-T Nonstore mode.
B TIMING AND ALTERNATE B SWEEP
The Alternate B Sweep circuitry, shown on Diagram 6,
produces a linear voltage ramp that drives the Horizontal
Preamplifier for Nonstore B Sweeps. The Alternate B
Sweep circuitry also produces the sweep-switching signals
that control the display of the A and B Nonstore Sweeps
and the gate signals used by the Intensity and Z-Axis cir
cuits to set the crt unblanking and intensity levels for the
Nonstore A Intensified and the B Sweep displays. The B
Gate signal goes to the Digital Time Base circuitry and is
the Storage trigger signal for B Delayed Horizontal Display
mode.
The B Sweep ramp is started by the B Sweep Logic
circuit either at the end of the set delay time (RUNS
AFTER DELAY) or when the first trigger signal occurs
after the delay time has elapsed (Trigger After Delay).
This delay time is a function of the B Delay Time Position
Comparator circuit and the A Sweep.
B M iller Sweep G enerator
The B Miller Sweep Generator is an integrator circuit
formed by Q709, Q710A, Q710B, Q712, and associated
timing components. This circuit produces the B Sweep sig
nal and works the same as the A Miller Sweep Generator.
See the "A Miller Sweep Generator” section for a descrip
tion of circuitry operation. The output at the collector of
Q712 drives the Horizontal Amplifier for Nonstore B
Sweeps and is applied to the B end-of-sweep transistor,
Q643.
B T rigg e r Level Com parator and S chm itt Trig ger
The B Trigger Level Comparator and Schmitt Trigger
are contained in U605. This circuit determines both the
trigger level and slope at which the B triggering signal is
produced. It functions in the same manner as the A
Trigger Level Comparator and Schmitt Trigger with the
exclusion of the TV trigger circuitry. See the “ A Trigger
Level Comparator and Schmitt Trigger" section for a
description of circuit operation. The +OUT terminal of
U605 is directly connected to the clock input of U670A to
initiate the B Sweep when the B Trigger is utilized.
Run A fte r Delay
The Run After Delay circuit lets the B Sweep Logic
start a B Sweep without the need for a B Trigger signal.
For the RUNS AFTER DELAY mode, B TRIGGER LEVEL
3-20
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