current through the timing capacitors, which results in a
linearly increasing voltage ramp as they charge. The ramp
is the A SWEEP output signal at the collector of Q706.
Parallel timing capacitors C702 and C703 remain in the
charging circuit for all SEC/DIV switch settings and are
used mostly for high sweep speeds. Capacitors C701A
and C701B are added in series at medium sweep speeds,
and C701B alone is added to the charging path for slow
sweep speeds.
When the ramp reaches approximately 12 V, the End-
of-Sweep Comparator transistor (Q525) becomes forward
biased. This action switches the A GATE HI and starts the
analog hold-off period. During hold off the A Sweep Gen
erator is reset. The A GATE signal going HI biases on
Q701, and the timing capacitors are fully discharged
before another sweep starts.
One end of timing resistor array R701 is connected to
the HOR REF signal, and the other end is connected to
the input of the Miller integrator by the SEC/DIV switch
contacts. The voltage applied to the timing resistor array
via the HOR REF signal varies with the setting of the
front-panel Variable SEC/DIV control (R721, located on
Diagram 7). The STORE mode time base is not affected
by the variable potentiometer setting. In the CAL position
of R721, a fixed reference level is applied to R701 to pro
duce the calibrated Nonstore sweep speed ranges. Switch
contacts actuated using the knob of R721 control the
STORE mode 4K/1K Compress and the XI0 MAG
features. The X I0 MAG feature works in both NONSTORE
and STORE.
Coded analog signals developed by circuitry connected
to the SEC/DIV switch contacts inform the Microprocessor
of the A SEC/DIV switch setting. The Microprocessor then
directs the Digital Time Base circuitry to set the correct
STORE mode sampling rate.
A Sweep Logic
The A Sweep Logic circuitry controls sweep generation,
as a function of incoming trigger signals and the A Trigger
mode selected.
Incoming trigger signals from the output of U460 clock
U502, a one-shot multivibrator, and cause the Q output of
U502 to go HI. If another trigger signal is not received by
U502 within the time limit determined by R503 and C501,
the Q output (U502 pin 3) will_go LO. Whenever trigger
signals are being received, the Q output of U502 biases on
Q509 to turn on DS518, the TRIG'D LED. The output of
Theory of Operation—2230 Service
U502 is also used in the Auto Baseline circuit as described
in the "P-P AUTO and TV FIELD” part of the discussion
that follows.
NORM. When NORM Trigger mode is selected, input
pin 12 of U532D is held HI by S401B, causing the gate
output to also be HI. The output of U532C is then LO, and
U506 pin 3 is not held HI. Input pin 4 of U532A is held HI
by S401C, causing the output to be LO, placing a LO on
input pin 7 of dual flip-flop U506. Trigger signals received
at input pin 6 (a clock input) of U506 then clock this LO to
the Q output (pin 2).
During the previous hold-off_period, U506 pin 2 was set
HI by U532B. This made the Q output (pin 3) LO. The LO
biased Q576 on, preventing the A Miller Sweep from run
ning. Whenever U506 pin 6 is clocked by a trigger signal
following hold off, the LO on the D input _(pin 7) is
transferred to the Q output (pin 2), and the Q output
(pin 3) goes HI. This biases Q576 off, and the A Miller
Sweep generates the sweep ramp as described in the pre
vious "A Miller Sweep Generator" discussion. When the
ramp voltage reaches about 12 V, End-of-Sweep transislor
Q525 is biased on. The output of U532B then changes
from LO to HI, setting U506 pin 2 HI and biasing on
A GATE transistor Q576. This triggers Hold-off One-shot
U504B to start the hold-off period, turning off Q525.
Transistor Q701 in the A Miller Sweep generator is also
biased on to discharge the timing capacitors during hold-
off time.
With U504B triggered, output pin 10 changes from LO
to HI, where it stays for a time set by the Hold-Off Timing
circuitry and the A SEC/DIV switch position. VAR HOLD-
OFF potentiometer R9521 sets the amount of current that
is available to charge C518, C519, or C520 to the thres
hold voltage on pin 14. During the time pin 10 is HI, pin 5
(the set input) of U506 is held HI so that trigger pulses
cannot start a new sweep. When pin 15 of U504B reaches
the threshold level on pin 14, pin 10 goes LO to end hold
off and release U506 from the set condition. The circuit is
then reset to start another sweep on the next trigger pulse
that appears at the clock input (pin 6) of U506. The holdoff
capacitors are switched by transistors Q7470 and Q7471
according to the states of the timing switch. Q7472 serves
as a dual diode to carry the discharge current. Logic sig
nals AC-1 and AC-2 provide part of the timing switch infor
mation for the I/O board, where their states are read at an
input port.
P-P AUTO and TV FIELD. When P-P Auto or TV Field
trigger is in use, the Auto Baseline circuitry is active.
Pin 12 of U532D is held LO by R569, and the output at
pin 9 follows the signal provided by the Q output of U502.
3-19
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