Theory of Operation—2230 Service
When reading data out of the RAM, the Display Con
troller has direct access to the memory address bus (RA).
RAM row and column addresses to be read from are
sequenced through in order. When a display data read is
taking place, the dynamic memory is refreshed by the
Display Controller.
When the Display Controller has completed a display
frame, it signals the Microprocessor (using the INTR sig
nal) that the last field is finished and awaiting the next
frame request. After the interrupt is received, the
Microprocessor can request the next frame (FRAME), then
the Display Controller resumes control of the RAM for the
next frame of data. When PROC RQ (U9208 pin 3) is HI,
the Display Controller is in the middle of a display cycle
and the Microprocessor is denied access to the display
RAM. The Microprocessor can request access to the
Display RAM using the PROC RQ (RAM SEG) signal line
to either write in new waveform data or read out data for
the Communication Option. The Display Controller allows
the Microprocessor to access the display RAM by setting
the PROCEN (U9208 pin 5) signal line LO. A LO
PROC EN signal enables the circuitry that allows the WR,
PA14, and PA15 signals, from the Microprocessor, to con
trol the display RAM. Even though the memory addresses
are under control of the Microprocessor, the RAS and
CAS signals are generated by the Display Controller.
YDAC and XDAC
Data from display controller U9208 is applied to X- and
Y-axis DACs U9210 and U9220. These DACs are biased
to provide output currents (approximately 0 to 2 mA) pro
portional to the digital data. R9214 and R9224 are adjust
ments to align the storage signals on the crt. The DAC
currents are applied to the Vector Generator along with
various control signals from U9208 via W6100.
VECTOR GENERATOR
Vector Generators
Vector Generator circuitry is shown on Diagram 20.
U6303 and U6304 convert the DAC currents into bipolar
voltages (approximately —2.5 V to +2.5 V) which are
applied to sample and hold circuits U6305 and U6306.
Outputs of the sample and hold circuits are applied to
integrator stages U6307 and U6308 through electronic
switches in U6301A and C. The integrator output signals
are continuously fed back to the sample and hold inputs,
causing these input voltages to be equal to the difference
between the drive inputs and the integrator outputs. When
the vector sample (VECT-SMPL) control line (via U6301B)
is actuated, the outputs of the sample and hold circuits
store these difference signals. Since the integrator output
slopes are proportional to these signals, the net result is
to effectively “connect the dots" which are equivalent to
the digital data values.
These circuits also have a “dot” mode available so that
the integrator outputs are stepped (dots) rather than con
tinuous (vectors). When the VECT/DOT signal is LO,
U6301A and C switch the integrator inputs directly to the
difference signals while also disconnecting the integration
capacitors C6315 and C6314. The feedback loops are thus
closed continuously, resulting in normal amplifier action.
Although the Vertical and Horizontal vector generators
operate the same, there are some differences between the
circuits and between their signal characteristics. To end up
with the proper signal polarities at the crt, X DAC U9210
(Horizontal) current is from 2 mA to 0 mA, while Y ,DAC
U9220 (Vertical) current is from 0 mA to 2 mA. Also, the
vertical integrator output is -2 V to +2 V while the hor
izontal integrator output is —2.5 V to +2.5 V. The
reduced vertical dynamic range allows proper interface to
the main deflection system. Since the vertical signal even
tually passes through the vertical delay line before reach
ing the crt, it is necessary to delay the horizontal signal as
well. This is done in the vector mode by delaying slightly
the vector sample signal applied to 1)6305 via R6320 and
C6312. In the dot mode the crt beam is blanked during the
transitions so the dots are only displayed after the signals
have arrived and settled.
VECTOR INTEGRATOR. The Y-axis (vertical) current
from the D/A Converter goes to the inverting input of
operational amplifier U6303. The amplifier is biased to pro
duce a bipolar output voltage, from -2.5 V to +2.5 V,
that is proportional to the input current. Negative feedback
from the parallel combination of R6303 and C6311 stabil
izes the amplifier.
Biasing of the non-inverting input of both the X-axis
and the Y-axis amplifiers is identical and supplied by a
resistive divider formed by R6304 and R6305 between
ground and the +5 V reference. Both resistors are equal
valued to produce a bias voltage of + 2.5 V. Resistor
R6308 provides a summing node for the input vector
current and the feedback current and develops the voltage
on the inverting input of U6303. Full current range of the
vector signal is from 0 to 2 mA. With no vector current in,
the feedback current supplies the full current through
R6308, and the output voltage of U6303 goes to -2 .5 V.
At maximum vector current input, the sum of the current
through R3608 must remain the same as with no vector
current; therefore the feedback current is reduced by the
amount of the vector current, and the output voltage goes
to +2.5 V.
SAMPLE-AND-HOLD. The voltage output of U6303 is
applied via R6309 to sample-and-hold circuit U6305.
Sample-and-Hold (S/H) switching is controlled by the
VECT SMPL signal from the Display Controller applied to
3-45
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