Tektronix 2230

Theory of Operation—2230 Service
control R602 is rotated fully clockwise. In this position of
R602, transistor Q637 is biased off, and a LO is present at
its collector. Inverter U660D then has a HI output at pin 8.
Resistor R640 provides positive feedback to obtain rapid
switching of the transistor. This HI output reverse biases
CR626 so that the state of U670A is determined by the
level at U660F pin 12.
If the B TRIGGER LEVEL control is not fully clockwise,
Q637 is biased on, and the B Sweep is in the triggerable-
after-delay mode. The output of U660D is then LO which
keeps the S input of U670A LO, preventing the flip-flop
from being set by the output of U660F.
Operation of the B Sweep Logic circuitry under both
triggering modes is described in the "B Sweep Logic” part
of the following discussion.
Delay Tim e Position Com parator
The Delay Time Position Comparator circuit compares
the amplitude of the A Sweep voltage ramp to the dc volt
age level set by the position of B DELAY TIME POSITION
potentiometer R9644. The output of the comparator
enables the B Sweep Logic circuit to start the B Sweep
after the end of the delay time.
The input voltages to Comparator U655 to be com
pared are the voltage from the wiper of B Delay Time
Position potentiometer R9644 and the A Sweep voltage
from the divider formed by R651, Delay Dial Gain poten
tiometer R652, and R653. Maximum and minimum input
voltages are established by VR645 and R646 respectively
for the noninverting input and by R652 for the inverting
input. Delay Start potentiometer R646 is adjusted in con
junction with Delay End potentiometer R652 to set the B
DELAY TIME POSITION crt readout calibration.
The comparator is controlled by the A ONLY gate sig
nal connected to pin 6. When the A ONLY signal is HI, the
comparator is able to make a comparison. While the A
Sweep signal on pin 3 is below the wiper voltage on pin 2,
the comparator output is at a HI level. When the A Sweep
ramp reaches the comparison level, the output at pin 7
goes LO. If A ONLY is LO, the comparator is switched to
a high impedance output state. The comparator output
level is then a HI that goes to pin 9 of NAND-gate latch
U680C and U680D.
B Sweep Logic
The B Sweep Logic circuitry utilizes signals from asso
ciated B Sweep circuitry to generate control signals for
both the B Miller Sweep and the B Z-Axis Switching Logic
circuits.
In the RUNS AFTER DELAY mode, the Run After
Delay circuit holds the D input of flip-flop U670A LO via
U660B. At the start of hold off when the A Sweep is reset,
U680D pin 13 is strobed with an Alt Sync pulse negative
transition. The output of the NAND-gate latch formed by
U680C and U680D is latched HI, and the output of U660F
goes LO. This places a LO on the S input of U670A and a
HI on the R input causing the flip-flop to reset. The LO on
pin 2 and a HI on pin 3 of U670A are converted to TTL
levels by Q630 and Q631. The resulting HI on the collector
of Q630 turns Q709 on. This discharges the B Miller
Sweep timing capacitors to reset the B Sweep Generator
and keeps a new B Sweep from starting. During the next
A Sweep ramp when the voltage at U655 pin 3 exceeds
the voltage at pin 2, the comparator output goes LO. The
NAND-gate latch changes output states and causes the
Set input of U670A to go HI. The LO on the Set input then
controls the flip-flop, and the Q output of U670A goes LO.
Shunting transistor Q709 shuts off, and the B Miller
Sweep Generator runs to produce a sweep ramp.
When the ramp voltage reaches a level of about 12 V,
B end-of-sweep transistor Q643 turns on and blanks the
rest of the B Sweep trace by reverse biasing CR817 in the
Z-Drive signal line (Diagram 9). The B Sweep Generator
continues to run either until the ramp reaches about 13 V,
at which time VR712 conducts to prevent the ramp volt
age from increasing further, or until the A Sweep ends. In
either case, the B Sweep generator is reset when the A
Sweep ends.
The B Sweep Generator becomes reset when the the
ALT SYNC signal goes from HI to LO to switch the output
state of the U680C-U680D latch._The Reset input of
U670A then goes LO, causing the Q output to switch HI
and reset the Sweep Generator. Depending on the set
tings of the A and B SEC/DIV switches, the A Sweep may
end before the B Sweep. In that case, the ALT SYNC sig
nal going LO at the end of the A Sweep immediately
resets the B Sweep Generator even if the sweep ramp
has not reached its maximum amplitude. A new B Sweep
starts the next time the B Delay Time Comparator goes
LO.
When not in the Runs After Delay mode, the output of
U660A is HI, and U670A has a HI on both the Set and the
D input. The circuitry connected to the Reset input of
U670A functions as described before. When the output of
U660F goes HI, U670A is no longer held reset. In this
case, the first B Trigger signal from the collector of Q630
after the end of the delay time clocks through the HI on
the D input, setting flip-flop U670A. The Q output of
U670A is then LO, and a B Sweep is started by reverse
biasing Q709 in the B Miller Sweep as before.
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