Theory of Operation—2230 Service
Alternate Display Switching Logic
The Alternate Display Switching Logic circuitry controls
both the Nonstore Horizontal Amplifier sweep switching
and the Nonstore Z-Axis Logic switching for A Inten and B
Only traces. The B Sweep ramp and gates are produced
for every A Sweep when the HORIZONTAL MODE is set
to either ALT or B. In ALT, the intensified zone on the A
Sweep trace is shown for one B Sweep interval, and dur
ing the next A Sweep interval, a B Sweep trace is
displayed during the B Sweep interval. For B Only traces,
the A Sweep must still run to produce the A gating signals
used throughout the circuitry for timing, but it is not
displayed.
HORIZONTAL MODE switch S648 selects the input
logic levels that drive the display switching circuitry. In the
A Horizontal mode, the Set input of U670B is LO, and the
Reset input is HI. This holds U670B reset with the A DISP
signal HI, passing only the A Sweep to the Horizontal
Amplifier (by the A Sweep selection transistor, Q742,
located on Diagram 7). In the B Horizontal mode, the set
input of U670B is HI, and the reset input is LO. This holds
U670B set with the B DISP signal HI, allowing only the B
Sweep to reach the Horizontal Amplifier (via the B Sweep
selection transistor, Q732).
With S648 set to ALT, and for all settings of the VERT-
ICAL MODE switches except BOTH-ALT, the VALT signal
applied to U660E is HI and the Set and Reset inputs of
U670B are both LO. The LO out of U660E causes the out
put of U680B to be HI. Each HI to LO transition of the
ALT SYNC signal applied to pin 1 of U680A causes the
NAND-gate output at pin 3_to change from LO to HI,
clocking U670B. The Q and Q outputs of U670B therefore
toggle, and the A DISP and B DISP signals cause the
sweep selection transistors (Diagram 7) to alternately pass
the A and B Sweep signals to the Horizontal Amplifier.
When the CH 1-BOTH-CH 2 VERTICAL MODE switch
(S550) is set to BOTH, the ADD-ALT-CHOP switch (S545)
becomes active. In the ALT VERTICAL MODE position,
the VALT signal is LO, the HALT signal is HI, and the
CH 1 SELECTED signal is a TTL square-wave signal that
switches states at the end of the A Sweep. Input pin 4 of
U680B is HI, and the gate output is the inverted CH 1
SELECTED signal. This output signal is combined with the
ALT SYNC signal by NAND-gate U680A to clock U670B.
Whenever the ALT SYNC signal goes LO at the end of a
sweep and the CH 1 SELECTED signal (at U680B pin 5)
switches from LO to HI, U670B is clocked. Since only
positive transitions on the clock input causes the flip-flop
to change output states, two A Sweeps must occur to
cause the flip-flop output levels to switch. Switching this
way, the crt first displays two A Intensified Sweeps, then
two Alternate B Sweeps.
SWP SEP. Whenever the B Sweep is selected to drive
the Horizontal Amplifier, the Q output of U670B is HI. This
HI goes to U665C pin 10 through Q683 and Q687, and
since pin 9 is also HI, the SEP signal from U665C is LO to
enable the A/B Sweep Separation circuitry (located on
Diagram 3).
B Z-Axis Logic
The B Z-Axis Logic circuitry switches signal current lev
els to drive the Z-Axis Amplifier for the Nonstore B Sweep
and the A Intensified Sweep displays. The current supplied
is summed with the other signal inputs on the Z-DRIVE
line to set the Nonstore display intensity levels.
With the HORIZONTAL MODE switch in the ALT posi
tion, pin 5 of U665B is HI. Then, the Q and Q outputs of
U670B, the B GATE signal from the output of U665D, and
the B INTENSITY potentiometer, set the intensity levels of
the Nonstore A Intensified and B Sweep traces. When the
A Sweep trace is displayed, the Q output of U670B is HI,
and the Q output is LO. These output levels bias Q683 on
and bias Q682 off. The collector voltage of Q683 reverse
biases CR817 to stop Z-Axis drive current from flowing
through the diode. With CR683 reverse biased, additional
Z-Axis drive current to intensify the A Sweep is supplied
whenever CR685 is biased off by the gating action of
U665B. Since input pin 5 of U665B is HI, the gate output
and therefore the conduction state of CR685 is set by the
B GATE signal from U660C. While the B GATE is HI, the
output of U665B is LO, and CR685 is biased off to add B
INTENS current to the Z-DRIVE line via CR816. During
periods that the B GATE is LO (B Sweep not running), the
output of U665B is HI, and CR685 is biased on. Diode
CR816 becomes reverse biased, and the extra current that
was being supplied to the Z-DRIVE line to intensify the A
Sweep is removed.
With the Q and Q outputs of U670B switched to display
the B Sweep (5 LO and Q HI), Q683 is biased off, and
Q682 is biased on. The collector voltage of Q682 reverse
biases CR816 to block any Z-Axis drive current from being
supplied through that diode. With CR687 off, the B Sweep
is displayed if CR680 is reverse biased. During the B
Sweep interval, the B GATE output at pin 11 of U665D is
LO. Diode CR680 is then reverse biased, and Z-Axis drive
current from 3 INTENS flows through CR817. If the B
Sweep is not running, the B GATE output of U665D is HI.
That HI forward biases CR680 and reverse biases CR817.
No B Z-AXIS drive current flows through CR817.
3-22
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