Theory of Operation—2230 Service
reset when the ACQENA signal is LO. ACQENA is clocked
HI by the CONV clock going HI (one-half CONV clock
cycle after CONV goes HI). Therefore WRITECLK, at the
Q output of U4104A, starts off LO at the beginning of an
acquisition period.
The gating circuit of the Clock Generator looks at the
states of ADCLK, CONV, and RNGB to set the active LO
K input of U4102B and U4104A. The J and K inputs of
U4104A have complemented signals applied from the logic
gating (J from NAND-gate U3112C and K from AND-gate
U4101B). When clocked, the flip-flop toggles for one state
of the applied J and K signals (J HI and K LO) and has no
change for the other (J LO and K HI). The WRITECLK and
WRITECLK outputs of the flip-flop are therefore at one-
half the CONV clock rate. The K signal from AND-gate
U4101B also goes to the K input of U4102B to set up
U4104A to either divide the ADCLK by two or just clock
ADCLK through. The CONV clock switches from 20 MHz
to 10 MHz when the SEC/DIV switch is switched from
10 ms to 20 ms while the ADCLK remains at 20 MHz for all
SEC/DIV switch settings.
Time Base Mode Register
The Microprocessor controls the Digital Time Base via
the Time Base Mode Register, U4119. Control bits are
latched into the register from the Data bus by the rising
edge of the signal on pin 11 of OR-gate U4114D. The out
put of U4114D pin 11 is normally HI, but when 10 2 and
address bit A5 are both made LO by the Microprocessor,
U4114D pin 11 goes LO. The data on the ADO through
AD7 bus lines then becomes valid. Either 10 2 or A5 going
HI then causes the signal on pin 11 to also go HI, latching
the data that is on the bus into the register. The outputs
are permanently enabled by the fixed LO on pin 1 of the
register.
Tim e Base Divider and Divider R egister
The Time Base Divider is formed by a chain of six pro
grammable counters (U4107-U4112). The Microprocessor
loads the counters to produce an output from the divider
that is a function of the SEC/DIV switch setting from 20 ms
to 5 s per division. Alternate sources of the SAVECLK are
selected at the fast sampling rates used for SEC/DIV
switch settings of 10 ms to 0.05 ms (see Table 3-3).
The Microprocessor writes the preloaded counts to the
Time Base Divider via time base Divider Register U4113
(see Table 3-4). A data byte is loaded into the counters of
the Time Base Divider chain by placing the data on the
Microprocessor Data Bus during I/O time segment 10 2.
After the data settles, the 10 2 signal goes HI. The rising
transition is gated through OR-gate U4114C to clock the
data into the register. The data bits loaded determine the
number of times the CONV 10 MHz clock is divided to pro
duce the SAVECLK frequency. Flip-flop U4125A divides
the output of the divider chain by two.
An external signal may be used to clock the digital
acquisition system. TTL level signals up to 1 kHz may be
applied to the EXT CLK INPUT connector on the instru
ment side panel. The external signal is applied to the D
input of flip-flop U4126A where it is clocked through to the
Q output on the rising edge of the WRITE clock. That Q
output is applied to the D input of flip-flop U4126B and
also clocked through by the rising edge of the WRITE
clock. The external clock is therefore delayed by two
WRITE clock periods and synchronized with the rising
edge of WRITE. The Q output of U4126B is applied to the
SAVECLK multiplexer where it is selected when the A
SEC/DIV switch is set to EXT CLK. External clock sym
metry is not critical, but each amplitude must remain
stable for at least 100 ns to acquire the waveform sample.
One sample of a sample pair is acquired on each half cycle
of the SAVECLK. As with the other clocking frequencies,
flip-flop U4125A divides the signal by two to produce the
SAVECLK frequency.
Record Counter
The Record Counter (U4115-U4117) determines when
the total number of data samples have been acquired to fill
the acquisition memory for triggered acquisitions. Depend
ing on the record length for the acquisition and the amount
of pretrigger, the Record Counters are preloaded with a
count that will cause full count (ENDREC) to be generated
when the record is full. When the acquisition starts, the
Acquisition Memory Address Counters count up to PRE
FULL. At that point, the Trigger Mux is enabled. After a
trigger arrives, the Clock Delay Timer generates TRIGD at
the next CONV clock, enabling the Record Counter. The
Record Counter counts RECCLK clocks until ENDREC
goes HI, stopping the acquisition (because the entire
record has been acquired).
Interrupt Logic
When selectively enabled by the Microprocessor, inter
rupts (INTR) are generated after a full record is acquired,
after a byte pair is acquired, or when a trigger occurs.
After the interrupt is generated, the Microprocessor polls
U3428 to find out what caused the interrupt.
RECORD INTERRUPT. Record interrupts are generated
each time a full record has been acquired in a triggered
acquisition mode. When Record Counter U4115-U4117
overflows and stops, the end of record signal ENDREC is
generated HI at U4105B pin 9. If the Microprocessor has
3-40
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