www.ti.com
Endpoints 1–5
soon as possible after the USBCS0.CLR_OUTPKT_RDY bit has been set. The USBCS0.INPKT_RDY is
cleared and an EP0 interrupt is generated when the data packet has been sent. Firmware might then load
more data packets as necessary. An EP0 interrupt is generated for each packet sent. Firmware must set
USBCS0.DATA_END in addition to USBCS0.INPKT_RDY when the last data packet has been loaded. This
starts the status stage of the control transfer.
EP0 switches to the IDLE state when the status stage has completed. The status stage may fail if the
USBCS0.SEND_STALL bit is set to 1. The USBCS0.SENT_STALL bit is then asserted, and an EP0
interrupt is generated.
If USBCS0.INPKT_RDY is not set when receiving an IN token, the USB controller replies with a NAK to
indicate that the endpoint is working, but temporarily has no data to send.
21.6.4 OUT Transactions (RX State)
If the control transfer requires data to be received from the host, the setup stage is followed by one or
more OUT transactions in the data stage. In this case, the USB controller is in the RX state and only
accepts OUT tokens. A successful OUT transaction comprises two or three sequential packets (a token
packet, a data packet, and a handshake packet
(2)
). If more than 32 bytes (maximum packet size) is to be
received, the data must be split into a number of 32-byte packets followed by a residual packet. If the
number of bytes to receive is a multiple of 32, the residual packet is a zero-length data packet, because a
data packet with payload less than 32 bytes denotes the end of the transfer.
The USBCS0.OUTPKT_RDY bit is set and an EP0 interrupt is generated when a data packet has been
received. The firmware should set USBCS0.CLR_OUTPKT_RDY when the data packet has been unloaded
from the EP0 FIFO. When the last data packet has been received (packet size less than 32 bytes)
firmware should also set the USBCS0.DATA_END bit. This starts the status stage of the control transfer.
The size of the data packet is kept in the USBCNT0 registers. Note that this value is only valid when
USBCS0.OUTPKT_RDY = 1.
EP0 switches to the IDLE state when the status stage has completed. The status stage may fail if the
DATA1 packet received is not a zero-length data packet or if the USBCS0.SEND_STALL bit is set to 1. The
USBCS0.SENT_STALL bit then is asserted and an EP0 interrupt is generated.
21.7 Endpoints 1–5
Each endpoint can be used as an IN only, an OUT only, or IN/OUT. For an IN/OUT endpoint, there are
basically two endpoints, an IN endpoint and an OUT endpoint associated with the endpoint number.
Configuration and control of IN endpoints is performed through the USBCSIL and USBCSIH registers. The
USBCSOL and USBCSOH registers are used to configure and control OUT endpoints. Each IN and OUT
endpoint can be configured as either an isochronous (USBCSIH.ISO = 1 and/or USBCSOH.ISO = 1) or
bulk/interrupt (USBCSIH.ISO = 0 and/or USBCSOH.ISO = 0) endpoint. Bulk and interrupt endpoints are
handled identically by the USB controller but have different properties from a firmware perspective.
The USBINDEX register must have the value of the endpoint number before the indexed endpoint registers
are accessed.
21.7.1 FIFO Management
Each endpoint has a certain number of FIFO memory bytes available for incoming and outgoing data
packets. Table 21-2 shows the FIFO size for endpoints 1–5. The firmware is responsible for setting the
USBMAXI and USBMAXO registers correctly for each endpoint to prevent data from being overwritten.
When both the IN and OUT endpoints of an endpoint number do not use double buffering, the sum of
USBMAXI and USBMAXO must not exceed the FIFO size for the endpoint. Figure 21-2 a) shows how the IN
and OUT FIFO memory for an endpoint is organized with single buffering. The IN FIFO grows down from
the top of the endpoint memory region, whereas the OUT FIFO grows up from the bottom of the endpoint
memory region.
(2)
For isochronous transfers, there is no handshake packet from the device.
195
SWRU191C–April 2009–Revised January 2012 USB Controller
Submit Documentation Feedback
Copyright © 2009–2012, Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
