191
* ADC10SSEL_0 -- ADC10OSC
* ADC10DIV_0 -- Divide by 1
* ~ISSH -- Input signal not inverted
* ~ADC10DF -- ADC10 Data Format as binary
* SHS_0 -- ADC10SC
* INCH_1 -- ADC Channel 1
*
* Note: ~<BIT> indicates that <BIT> has value zero
*/
ADC10CTL1 = CONSEQ_2 | ADC10SSEL_0 | ADC10DIV_0 | SHS_0 | INCH_1;
/* Analog (Input) Enable Control Register 0 */
ADC10AE0 = 0x2;
/*
* Data Transfer Control Register 0
*
* ~ADC10TB -- One-block transfer mode
* ADC10CT -- Data is transferred continuously after every conversion
*
* Note: ~ADC10TB indicates that ADC10TB has value zero
*/
ADC10DTC0 = ADC10CT;
/* Data Transfer Control Register 1 */
ADC10DTC1 = no_of_samples;
/* Data Transfer Start Address */
ADC10SA = ((unsigned int)adc_pointer);
/* enable ADC10 */
ADC10CTL0 |= ENC;
/* USER CODE START (section: ADC10_graceInit_epilogue) */
/* User code */
/* USER CODE END (section: ADC10_graceInit_epilogue) */
}
void System_graceInit(void)
{
/* USER CODE START (section: System_graceInit_prologue) */
/* User initialization code */
/* USER CODE END (section: System_graceInit_prologue) */
/* Clear oscillator fault flag with software delay */
do
{
// Clear OSC fault flag
IFG1 &= ~OFIFG;
// 50us delay
__delay_cycles(400);
} while (IFG1 & OFIFG);
/*
* SR, Status Register
*
* ~SCG1 -- Disable System clock generator 1
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