313
/*
* Basic Clock System Control 3
*
* XT2S_0 -- 0.4 - 1 MHz
* LFXT1S_0 -- If XTS = 0, XT1 = 32768kHz Crystal ; If XTS = 1, XT1 = 0.4 - 1-
MHz crystal or resonator
* XCAP_1 -- ~6 pF
*/
BCSCTL3 = XT2S_0 | LFXT1S_0 | XCAP_1;
/* USER CODE START (section: BCSplus_graceInit_epilogue) */
/* User code */
/* USER CODE END (section: BCSplus_graceInit_epilogue) */
}
void USCI_B0_graceInit(void)
{
/* USER CODE START (section: USCI_B0_graceInit_prologue) */
/* User initialization code */
/* USER CODE END (section: USCI_B0_graceInit_prologue) */
/* Disable USCI */
UCB0CTL1 |= UCSWRST;
/*
* Control Register 0
*
* ~UCA10 -- Own address is a 7-bit address
* ~UCSLA10 -- Address slave with 7-bit address
* ~UCMM -- Single master environment. There is no other master in the system.
The address compare unit is disabled
* UCMST -- Master mode
* UCMODE_3 -- I2C Mode
* UCSYNC -- Synchronous Mode
*
* Note: ~<BIT> indicates that <BIT> has value zero
*/
UCB0CTL0 = UCMST | UCMODE_3 | UCSYNC;
/*
* Control Register 1
*
* UCSSEL_2 -- SMCLK
* ~UCTR -- Receiver
* ~UCTXNACK -- Acknowledge normally
* ~UCTXSTP -- No STOP generated
* ~UCTXSTT -- Do not generate START condition
* UCSWRST -- Enabled. USCI logic held in reset state
*
* Note: ~<BIT> indicates that <BIT> has value zero
*/
UCB0CTL1 = UCSSEL_2 | UCSWRST;
/* I2C Slave Address Register */
UCB0I2CSA = DS1307_address;
/* Bit Rate Control Register 0 */
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