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TMS570LS0714
SPNS226E –JUNE 2013–REVISED NOVEMBER 2016
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System Information and Electrical Specifications Copyright © 2013–2016, Texas Instruments Incorporated
The parity protection for peripheral RAMs is not enabled by default and must be enabled by the
application. Each individual peripheral contains control registers to enable the parity protection for
accesses to its RAM.
NOTE
The CPU read access gets the actual data from the peripheral. The application can choose
to generate an interrupt whenever a peripheral RAM parity error is detected.
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