ZED-F9P-Integration Manual
UBX-18010802 - R02
4 Receiver description Page 37 of 114
Advance Information
Figure 22: DDC Random Read Access
The format of the current address read request is :
Figure 23: DDC Current Address Read Access
4.5.5.2 Write Access
The receiver does not provide any write access except for writing UBX and NMEA messages to the
receiver, such as configuration or aiding data. Therefore, the register set mentioned in section Read
Access is not writeable. Following the start condition from the master, the 7-bit device address and
the RW bit (which is a logic low for write access) are clocked onto the bus by the master transmitter.
The receiver answers with an acknowledge (logic low) to indicate that it is responsible for the given
address. Now, the master can write 2 to N bytes to the receiver, generating a stop condition after the
last byte being written. The number of data bytes must be at least 2 to properly distinguish from
the write access to set the address counter in random read accesses.
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