u-blox ZED-F9P - Page 5

ZED-F9P-Integration Manual
UBX-18010802 - R02

Contents Page 5 of 114
Advance Information
4.14.4 Parsing the signature...............................................................................................................66
4.14.5 Calculate the hash.................................................................................................................... 66
4.15 Spoofing detection.............................................................................................................................67
4.15.1 Introduction.................................................................................................................................67
4.15.2 Scope............................................................................................................................................67
4.16 Timemark............................................................................................................................................. 67
5 Hardware description........................................................................................................ 69
5.1 Block diagram........................................................................................................................................ 69
5.2 Connecting power.................................................................................................................................69
5.2.1 VCC: Main supply voltage.......................................................................................................... 69
5.2.2 V_BCKP: Backup supply voltage...............................................................................................70
5.2.3 ZED-F9P Power supply............................................................................................................... 70
5.3 Interfaces................................................................................................................................................71
5.3.1 UART interfaces...........................................................................................................................72
5.3.2 SPI interface..................................................................................................................................73
5.3.3 D_SEL interface............................................................................................................................73
5.3.4 RESET_N interface...................................................................................................................... 73
5.3.5 SAFEBOOT_N interface..............................................................................................................73
5.3.6 TIMEPULSE interface................................................................................................................. 73
5.3.7 TX_READY interface....................................................................................................................73
5.3.8 USB interface................................................................................................................................73
5.3.9 Display Data Channel (DDC)......................................................................................................75
5.3.10 Antenna supervisor...................................................................................................................75
5.3.11 EXTINT......................................................................................................................................... 78
6 EOS/ESD precautions........................................................................................................79
6.1 ESD handling precautions.................................................................................................................. 79
6.2 ESD protection measures...................................................................................................................79
6.3 EOS precautions................................................................................................................................... 80
6.4 Safety precautions............................................................................................................................... 80
7 Electromagnetic interference on I/O lines..................................................................81
7.1 General notes on interference issues.............................................................................................. 81
7.2 In-band interference mitigation........................................................................................................ 82
7.3 Out-of-band interference....................................................................................................................82
8 Design..................................................................................................................................... 83
8.1 Pin assignment..................................................................................................................................... 83
8.2 RF front-end circuit options...............................................................................................................85
8.3 Antenna...................................................................................................................................................86
8.4 Stacked patch antenna.......................................................................................................................87
8.5 ZED-F9P minimal design.................................................................................................................... 91
8.6 ZED-F9P antenna bias........................................................................................................................ 92
8.7 Layout......................................................................................................................................................93
8.7.1 Placement......................................................................................................................................93
8.7.2 Package footprint, copper and solder mask.......................................................................... 94
8.8 Layout guidance....................................................................................................................................97
8.8.1 RF In trace..................................................................................................................................... 97
8.8.2 Vias for the ground pads........................................................................................................... 99
8.8.3 VCC pads....................................................................................................................................... 99
8.9 Design in checklist............................................................................................................................. 100