Xerox PHASER 3435 - Page 207

General Procedures and Information
Phaser 3435 5/08 6-21
Asic(SPGPv3)
• CPU Core: ARM1020E
-32KB instruction cache and 32KB data cache
• Operating Frequency
-CPU Core: over 300MHz
-System Bus: 100MHz
•SDRAMC
-32Bits Only, 100MHz
-5 Banks (Up to 128MB per Bank)
• ROMC
-4 Banks (Up to 16MB per Bank)
• IOC
-6 Banks (Up to 16MB per Bank
• DMAC
-4 Channels
• HPVC
-Dual/Single Beam
-LVDS Pad (VDO, HSYNC)
• UART
-5 Channels (1 Channels Supports DMA Operation)
• PCI Controller
-32Bits, 33/66MHz
-PCI Local Bus Specification rev2.2 Complaint
-Host / Agent Mode (Support 4 Devices in Host Mode)
• NAND Flash Controller
-8/16Bits, H/W EEC Generation
-Auto Boot Mode (Using Internal SRAM, 4KB)
•MAC
-10M/100Mbps
-Full IEEE 802.3 Compatibility
• Engine Controller
-LSU Interface Unit
-Step Motor: 2 Channels
-PWM: 8 Channels
-ADC: 6 Channels
• I2C Controller
-I2C(S-BUS) Slave Device Support(I2C Version 2.1)
• RTC
-RTC Core Voltage: 3V PLL
-3 PLL: MAIN, PCI, PVC