Spartan-3E Starter Kit Board User Guide www.xilinx.com 97
UG230 (v1.0) March 9, 2006
Configuring from SPI Flash
R
Insert Jumper on JP8 and Hold PROG_B Low
The JTAG parallel programming cable directly accesses the SPI Flash pins. To avoid signal
contention with the FPGA, ensure that the connecting FPGA pins are high-impedance.
Force the FPGA’s PROG_B pin Low by installing a jumper on JP8, next to the PROG push
button, as shown in Figure 12-16. See Figure 12-3, page 90 to locate jumper JP8 and
surrounding landmarks.
Re-apply power to the Spartan-3E Starter Kit board.
Figure 12-15:
Attaching a JTAG Parallel Programming Cable to the Board
Table 12-2:
Cable Connections to J12 Header
Cable and Labels Connections
J12 Header Label SEL SDI SDO SCK GND VCC
JTAG3 Cable Label TMS TDI TDO TCK GND VCC
Flying Leads Label
TMS/
PROG
TDI/
DIN
TDO/
DONE
TCK/
CCLK
GND/
GND
VREF/
VREF
UG230_c15_14_030206
a) JTAG3 Parallel Connector b) Parallel Cable III or Parallel Cable IV
with Flying Leads
Figure 12-16:
Installing the JP8 Jumper Holds the FPGA in Configuration State
PROG
GND
JP8
PROG
PROG
GND
DEFAULT
NO JUMPER
JP8
PROG
DEFAULT
NO JUMPER
UG230_c15_15_030206
a) No Jumper: FPGA Operational (default) b) Jumper Installed: FPGA Held in
Configuration State, I/Os in High Impedance
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