Xilinx Spartan-3E User Manual

Spartan-3E Starter Kit Board User Guide www.xilinx.com 89
UG230 (v1.0) March 9, 2006
R
Chapter 12
SPI Serial Flash
The Spartan-3E Starter Kit board includes a STMicroelectronics M25P16 16 Mbit SPI serial
Flash, useful in a variety of applications. The SPI Flash provides an alternative means to
configure the FPGA—a new feature of Spartan-3E FPGAs as shown in Figure 12-1. The SPI
Flash is also available to the FPGA after configuration for a variety of purposes, such as:
• Simple non-volatile data storage
• Storage for identifier codes, serial numbers, IP addresses, etc.
• Storage of MicroBlaze processor code that can be shadowed into DDR SDRAM.
UCF Location Constraints
Figure 12-2 provides the UCF constraints for the SPI serial Flash PROM, including the I/O
pin assignment and the I/O standard used.
Figure 12-1: Spartan-3E FPGAs Have an Optional SPI Flash Configuration Interface
Table 12-1: SPI Flash Interface Signals
Signal FPGA Pin Direction Description
SPI_MOSI T4 FPGAÆSPI Serial data: Master Output, Slave Input
SPI_MISO N10 FPGAÅSPI Serial data: Master Input, Slave Output
SPI_SCK U16 FPGAÆSPI Clock
SPI_SS_B U3 FPGAÆSPI Asynchronous, active-Low slave select input
(T4)
SPI_MOSI
(N10)
(U16)
(U3)
Spartan-3E FPGA
SPI_MISO
SPI_SCK
SPI_SS_B
D
C
Q
S
STMicro M25P16
SPI Serial Flash
CCLK
DIN/D0
MOSI/CSI_B
CSO_B
UG230_c15_01_030206
Figure 12-2: UCF Location Constraints for SPI Flash Connections
# some connections shared with SPI Flash, DAC, ADC, and AMP
NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 ;
NET "SPI_MOSI" LOC = "T4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "SPI_SS_B" LOC = "U3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "SPI_ALT_CS_JP11" LOC = "R12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;

Xilinx Spartan-3E Specifications

General

Brand	Xilinx
Model	Spartan-3E
Category	Motherboard
Language	English