Xilinx Virtex UltraScale+ FPGAs User Manual

Ports and Attributes
The table below lists ports required by the TX inializaon process.
Table 14: TX Initialization and Reset Ports
Port Dir
Clock
Domain
Description
CH[0/1]_GTTXRESET In Async This port is driven High and then deasserted to start a TX reset
sequence. The components to be reset are determined by
TXPMARESETMASK and TXPCSRESETMASK. In sequential mode,
the resets are performed sequentially. In single mode, the
resets are performed simultaneously.
CH[0/1]_TXRESETMODE[1:0]
In Async Reset mode port for TX:
2’b00: Sequential mode (recommended).
2’b01: Reserved.
2’b10: Reserved.
2’b11: Single mode.
CH[0/1]_TXPMARESETMASK[1:0]
In Async TX PMA reset mask selection:
Bit 1: TX PMA.
Bit 0: CKCAL.
CH[0/1]_TXPCSRESETMASK[1:0] In Async TX PCS reset mask selection
Bit 1: TX PCS.
Bit 0: TX FEC.
CH[0/1]_TXUSERRDY In Async This port is driven High by the user application when TXUSRCLK
is stable.
CH[0/1]_TXPMARESETDONE Out Async This active-High signal indicates TX PMA reset is complete.
CH[0/1]_TXRESETDONE Out TXUSRCLK This active-High signal indicates the GTM transceiver TX has
finished reset and is ready for use. This port is driven Low when
GTTXRESET goes High and is not driven High until the GTM
transceiver has completed all TX reset steps.
CH[0/1]_ TXCKALRESET In Async This port is driven High and then deasserted to start a single
mode reset on TX CKCAL. The reset is not dependent on
TXRESETMODE or TXPMARESETMASK setting.
CH[0/1]_ TXPMARESET In Async This port is driven High and then deasserted to start a single
mode reset on TX PMA. The reset is not dependent on
TXRESETMODE or TXPMARESETMASK setting.
CH[0/1]_ TXFECRESET In Async This port is driven High and then deasserted to start a single
mode reset on TX FEC. The reset is not dependent on
TXRESETMODE or TXPCSRESETMASK setting.
CH[0/1]_ TXPCSRESET In Async This port is driven High and then deasserted to start a single
mode reset on TX PCS. The reset is not dependent on
TXRESETMODE or TXPCSRESETMASK setting.
Chapter 2: Shared Features
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 28
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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English