Xilinx Virtex UltraScale+ FPGAs User Manual

The following table lists aributes required by GTM transceiver TX inializaon. In general cases,
the reset me required by the TX PMA or the TX PCS varies depending on line rate. The factors
aecng PMA reset me and PCS reset me are the user-congurable aributes
TX_PMA_RESET_TIME, TX_PCS_RESET_TIME, TX_CKCAL_RESET_TIME, and
TX_FEC_RESET_TIME.
Table 15: TX Initialization and Reset Attributes
Attribute Type Description
CH[0/1]_RST_TIME_CFG0 16-bit Reserved.
Bit Name Address Description
TX_PCS_RESET_TIME [14:10] Represents the time duration to apply a TX PCS reset. Use
the recommended value from the Wizard. Must be a non-
zero value when TXPCSRESETMASK[1] is High and
GTTXRESET initiates the reset process.
TX_PMA_RESET_TIME [9:5] Represents the time duration to apply a TX PMA reset. Use
the recommended value from the Wizard. Must be a non-
zero value when TXPMARESETMASK[1] is High and
GTTXRESET initiates the reset process.
TX_CKCAL_RESET_TIME [4:0] Represents the time duration to apply a TX CLKGEN reset.
Use the recommended value from the Wizard. Must be a
non-zero value when TXPMARESETMASK[0] is High and
GTTXRESET initiates the reset process.
CH[0/1]_RST_TIME_CFG1 16-bit Reserved.
Bit Name Address Description
TX_FEC_RESET_TIME [4:0] Represents the time duration to apply a TX CKCAL reset.
Use the recommended value from the Wizard. Must be a
non-zero value when TXPMARESETMASK[0] is High and
GTTXRESET initiates the reset process.
CH[0/1]_RST_LP_CFG0 16-bit Reserved.
Bit Name Address Description
TX_PCS_RESET_LOOP_ID [11:8] Reserved. Use the recommended value from the Wizard.
TX_PMA_RESET_LOOP_ID [7:4] Reserved. Use the recommended value from the Wizard.
TX_CKCAL_RESET_LOOP_ID [3:0] Reserved. Use the recommended value from the Wizard.
TX_FEC_RESET_LOOP_ID [15:12] Reserved. Use the recommended value from the Wizard.
CH[0/1]_RST_LP_ID_CFG1 16-bit Reserved.
Bit Name Address Description
TX_PCS_LOOPER_END_ID [15:12] Reserved. Use the recommended value from the Wizard.
TX_PCS_LOOPER_START_ID [11:8] Reserved. Use the recommended value from the Wizard.
TX_PMA_LOOPER_END_ID [7:4] Reserved. Use the recommended value from the Wizard.
TX_PMA_LOOPER_START_ID [3:0] Reserved. Use the recommended value from the Wizard.
CH[0/1]_RST_LP_CFG4 1-bit Reserved.
Bit Name Address Description
BYP_HDSHK_TX_PCS_RESET_LOOP [3] Reserved. Use the recommended value from the Wizard.
BYP_HDSHK_TX_CKCAL_RESET_LOOP [0] Reserved. Use the recommended value from the Wizard.
Chapter 2: Shared Features
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 29
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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English