Xilinx Virtex UltraScale+ FPGAs - Page 74

Figure 34: TX Serial and Parallel Clock Divider
IBUFDS_GTM
MGTREFCLKP
MGTREFCLKN
ODIV2
O
REFCLK_HROW_CK_SEL
REFCLK
Distribution
REFCLK SEL
LCPLL
TX CLKGEN
TX PROG
DIV
PISO
CH[0/1]_TXPROGDIVCLK
TXP/N
TX DATA
Polarity
Control
TX PCSTX PMA
TX DATA from
Upstream PCS Blocks
Output Clock to BUFG_GT
Output to
GTM_DUAL
GTM_DUAL (GTM Transceiver Primitive)
/32
Pre-
Coder
Gray
Encoder
TX FIFO
CH[0/1]_TXUSRCLK
X20915-110218
Notes relevant to the gure:
1. CH[0/1]_TXPROGDIVCLK is used as the source of the interconnect logic clock via BUFG_GT.
2. There is only one LCPLL in the GTM_DUAL primive, which is shared between the TX/RX.
TX Programmable Divider
The TX programmable divider shown in Figure 34 uses the LCPLL output clock to generate a
parallel output clock. By using the transceiver LCPLL, TX programmable divider, and BUFG_GT,
CH[0/1]_TXPROGDIVCLK should be used as a clock source for the interconnect logic.
The following tables show the programmable divider ports and aributes, respecvely.
Chapter 3: Transmitter
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 74
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