4-26 Troubleshooting
0x31 Program DRAM throttling and throttling event registers
0x32 Setup DRAM control register for normal operation and enable
0x33 Enable RCOMP
0x34 Clear DRAM initialization bit in the SB
0x35 Initialization Sequence Completed, program graphic clocks
0x43 Program Thermal Throttling
Table 4-4. BDS & Specific action:
Phase
POST Code Range
0x00 Report the legacy boot is happening
0x12 Wake up the Aps
0x13 Initialize SMM Private Data and relocate BSP SMBASE
0x21 PC init begin at the stage1 re
0x27 Report every memory range do the hard ware ECC init
0x28 Report status code of every memory range
0x50 Get the root bridge handle twa
0x51 Notify pci bus driver starts to program the resource
0x58 Reset the host controller Sof
0x5A e IdeBus begin initialization
0x79 Report that the remote terminal is being disabled
0x7A Report that the remote terminal is being enabled
0x90 Keyboard reset
0x91 USB Keyboard disable
0x92 Keyboard detection
0x93 Report that the usb keyboard is being enabled
0x94 Clear the keyboard buffer
0x95 Init Keyboard
0x98 Mouse reset
0x99 Mouse disable
0x9A Detect PS2 mouse
0x9B Report that the mouse is being enabled
0xB8 Peripheral removable media reset(ex:IsaFloppy, USB device)
Table 4-3. DEBUG_BIOS equ 1
(Chipset\Alviso\MemoryInitAsm\IA32\IMEMORY.INC) (Continued)
Phase POST Code Range
SG_JE50_HR.book Page 26 Thursday, December 23, 2010 3:47 PM
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