4-28 Troubleshooting
0xAF PEI_DXE_IPL
Table 4-6. Each Driver entry point used in 80_PORT
Phase POST Code Range
0x30 RESERVED
0xB6 DXE_CRC32_SECTION_EXTRACT
0xB8 SCRIPT_SAVE
0xB9 ACPI_S3_SAVE
0xBA SMART_TIMER
0xBB JPEG_DECODER
0xBC PCX_DECODER
0xBE HT_CPU / MP_CPU
0xBF LEGACY_METRONOME
0xC0 FTWLITE
0xC1 RUN_RIME
0xC2 MONOTONIC_COUNTER
0xC3 WATCH_DOG_TIMER
0xC4 SECURITY_STUB tw
0xC5 DXE_CPU_IO
0xC6 CF9_RESET Sof
0xC7 e PC_RTC
0xC8 STATUS_CODE
0xC9 VARIABLE EMU_VARIABLE
0xD9 DXE_CHIPSET_INIT
0x45 DXE_ALERT_FORMAT
0xD6 PCI_HOST_BRIDGE
0xD7 PCI_EXPRESS
0xD5 DXE_SB_INIT
0xDA IDE_CONTROLLER
0xDB SATA_CONTROLLER
0xDD SB_SM_BUS
0xE7 ISA_ACPI_DRIVER
Table 4-5. Each PEIM entry point used in 80_PORT (Continued)
Phase POST Code Range
SG_JE50_HR.book Page 28 Thursday, December 23, 2010 3:47 PM
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