ADAV4601 System Design Document Confidential Information
Rev.1 August 2009 Analog Devices Page 94
Bit No. Bit Name Description Default
Bits[8:7] BCLK frequency
(master)
Used to set the BCLK frequency when the synchronous serial port is in
master mode.
00
00b = 64 × frequency sample, FS, (3.072 MHz)
01b = 128 × FS (6.144 MHz)
10b = 256 × FS (12.288 MHz)
11b = reserved
Bits[6:5] Reserved Always write as 0 if writing to this register. 00
Bit[4] Dither enable When set to 1, it performs dithering on the digital output when
the word width
is set to 20 bits or 16 bits. This reduces the effect of truncation
noise.
0
0b = disabled
1b = enabled
Bits[3:2] Synchronous port
clock select
Used to select the serial clocks used for the synchronous digital
inputs.
0
00b = uses LRCLK0 and BCLK0
01b = uses LRCLK1 and BCLK1
10b = uses LRCLK2 and BCLK2
11b = reserved
Bit[1] 8ch TDM enable When set to 1, Time Division Multiplexing mode is enabled. 0
0b = disabled
1b = enabled
Bit[0] Reserved Always write as 0 if writing to this register. 0
Address 0x000D Reserved (Default: 0x0721)
Address 0x0018 Audio Mute Control 1 Register (Default: 0x7F00)
Table 48.
Bit No. Bit Name Description Default
Bits[15:8] PWM output
latency
Set the delay from the 50/50 duty-cycle square wave to zero on GND
when the output
is muted and Bit[5] is set to 1.
01011111
0x00 = 1.066 ms
0x01 = 2.133 ms
…
0x5F = 101.33 ms
…
0xFE = 270.93 ms
0xFF = 272 ms
Bits[7:6] Reserved Always write as 0 if writing to this register. 00
Bit[5] PWM zero
enable
Used to specify the final condition of the PWM channels after a mute. 0
0b = PWM not zeroed after audio mute
1b = PWM zeroed after audio mute
Bit[4] Mute clear select Mute clear select bit. When the mute pin is used to mute the device,
the part can be
unmuted in two ways, depending on the condition of this bit.
0
0b = mute pin rising edge clears mute bit
1b = mute clear gated by clear mute bit
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