ADAV4601 System Design Document Confidential Information
Rev.1 August 2009 Analog Devices Page 99
APPENDIX B – LAYOUT RECOMMENDATIONS
DECOUPLING
The following pins must be decoupled to ground with the following priority
•
VREF
•
FILTA
•
FILTD
•
PLL_LF
•
SUPPLIES (AVDD, DVDD, ODVDD)
All the Ceramic Bypass Capacitors must be decoupled to the corresponding GND pins before seeing the ground
plane. See Figure 75 for more details.
Figure 75: Ceramic Decoupling Capacitors
The ceramic capacitors should be placed as close to the ADAV4601 as possible, governed by the priority listing
above. The larger electrolyte capacitors should then placed as closed to the ADAV4601 as possible in the same
priority as listed above.
In addition, the 1nF and 100nF ceramic capacitors for the PLL Loop Filter should both be placed as close as possible
to the ADAV4601.
Note: If a ceramic capacitor has to be placed on the underside of the evaluation board, ensure there is a keep out
put around the via to ensure the pin sees the cap first. Do not leave the pin see the ground plane first. See the
above figure for more details regarding this.
CRYSTAL OSCILLATOR CIRCUIT
Traces for the oscillator circuit should be kept as short as possible to avoid any possible fluctuations in the crystal
frequency due to parasitic capacitance. In addition, avoid long board traces connected to any of these components
because such traces may affect crystal start-up and operation.
Cap is the first
thing pin sees
Keep out around via where
decoupling caps are on reverse side
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