ARM MPS2 User Manual

Note
See Application Note AN387 Arm
®
Cortex
®
-M0 Design Start SMM on V2M-MPS2 for an example scc.v
file that implements these registers.
Note
If the FPGA does not implement an SCC interface, Arm recommends that you tie off the
CFGDATAOUT and nRSTREQ signals as follows:
• Tie the CFGDATAOUT signal from the FPGA LOW.
• Tie the nRSTREQ signal from the FPGA HIGH.
Related information
2.16 Minimum design settings for board operation on page 2-47
2.13.2 SCC READ and WRITE operations
During WRITE operations, after clocking in the address and data, CFGLOAD loads the address and
data into the SCC. The MCC clocks the WRITE DATA Most Significant Bit (MSB) first.
During READ operations, after clocking in the address, CFGLOAD loads the read address into the SCC.
The SCC clocks the READ DATA Least Significant Bit (LSB) first.
2.13.3 SCC READ and WRITE timings
The following figure shows the timings for the WRITE operation.
CFGCLK
CFGLOAD
nCFGRST
CFGWnR
SCC
reset
Write address Write data
Load address
and data
A11
A10 A0 D31 D30 D0
CFGDATAIN
D1
A9
Figure 2-15 MCC write to SCC
The following figure shows the timings for the READ operation.
A11 A10
CFGCLK
A0
D0 D1 D31
CFGDATAIN
D30
A9
CFGLOAD
nCFGRST
CFGWnR
SCC
reset
Write address Read data
Load
address
CFGDATAOUT
Figure 2-16 MCC read from SCC
The following table shows the MCC AC timing requirements.
2 Hardware Description
2.13 MCC FPGA serial interface
100112_0200_09_en Copyright © 2013–2016, 2018–2020 Arm Limited or its affiliates. All
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ARM MPS2 Specifications

General

Brand	ARM
Model	MPS2
Category	Computer Hardware
Language	English