2.16 Minimum design settings for board operation
You must implement a minimum amount of RTL in the FPGA for theMPS2 or MPS2+ FPGA
Prototyping Board to operate correctly.
You must tie off the following FPGA signals to generate the minimum RTL in the FPGA for correct
operation:
1. Set the following signals to the inactive HIGH state:
• SMB_PSRAM_nce[1:0].
• SMB_ETH_nCS.
• SSRAM1_nCE1.
• SSRAM2_nCE1
• SSRAM3_nCE1
2. Set the SMB chip select to the inactive HIGH state by tying the chip selects SMB_nCS to
0b11111111.
3. Set the CFGDATAOUT signal to the inactive LOW state by tying NAND_D[5] to 0b0.
Note
This informs the MCC that the board does not implement any of its features.
4. Set the nRSTREQ to the inactive HIGH state by tying NAND_D[7] to 0b1.
Note
This prevents nRSTREQ from generating a reset. nRSTREQ is usually a system-wide master soft
reset signal that is both generated and observed by the JTAG debug box.
Note
Arm recommends that you tie all unused pins to their inactive states.
Related information
2.13.1 Serial Configuration Controller (SCC) on page 2-39
2 Hardware Description
2.16 Minimum design settings for board operation
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