4.3 Register summary
This section summarizes the MPS2 and MPS2+ SCC registers and system configuration registers
characteristics.
The following table shows the registers in offset order from the base memory address.
Table 4-1 MPS2 and MPS2+ SCC register summary
Offset Name Type Reset Width Comment
0x000
SCC_CFG0 RW
0x00000000
32 Remaps block RAM to ZBT.
0x004
SCC_CFG1 RW
0x00000000
32 Controls the MCC user LEDs.
0x008
- - - - Reserved. Do not write to or read from this register.
0x00C
SCC_CFG3 RO
0x00000000
32 Denotes the state of the MCC user switches.
0x010
SCC_CFG4 RO
0x00000000
32 Denotes the board revision.
0x014 - 0x09C - - - - Reserved. Do not write to or read from these registers
0x0A0
SYS_CFGDATA_RTN RO
0x00000000
32 This is one oUser data return register for reads from board
peripherals.
0x0A4
SYS_CFGDATA_OUT RW
0x00000000
32 User data output register for writes to board peripherals.
0x0A8
SYS_CTRL RW
0x00100000
32 Control register. Controls read and write operations.
0x0AC
SYS_CFGSTAT RO
0x00000000
32 Status register. Shows status of read and write operations.
0x0AD - 0x0FC - - - - Reserved. Do not write to or read from these registers.
0x100
SCC_DLL RO
0xFFFC0000
32 DLL Lock Register
0x104 - 0xFF7 - - - - Reserved. Do not write to or read from these registers
0xFF8
SCC_AID RO
0x03100708
32 Contains the FPGA build number, the target board of the
FPGA build, and information about the SCC register
implementation.
0xFFC
SCC_ID RO
0x4104XXX1
32 Contains information about the FPGA image.
Related information
2.13 MCC FPGA serial interface on page 2-39
4.4.2 SCC_CFG0 Register on page 4-63
4.4.3 SCC_CFG1 Register on page 4-64
4.4.4 SCC_CFG3 Register on page 4-64
4.4.5 SCC_CFG4 Register on page 4-65
4.5.2 SYS_CFGDATA_RTN Register on page 4-70
4.5.3 SYS_CFGDATA_OUT Register on page 4-71
4.5.4 SYS_CFGCTRL Register on page 4-72
4.5.5 SYS_CFGSTAT Register on page 4-73
4.4.6 SCC_DLL Register on page 4-66
4.4.7 SCC_AID Register on page 4-67
4.4.8 SCC_ID Register on page 4-68
4 Programmers Model
4.3 Register summary
100112_0200_09_en Copyright © 2013–2016, 2018–2020 Arm Limited or its affiliates. All
rights reserved.
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