Purpose
Determines the state of the eight user switches on the MPS2 and MPS2+ FPGA Prototyping
Boards. The MCC polls the switches and updates this SCC register in the FPGA.
Usage constraints
The SCC_CFG3 Register is read-only.
Configurations
Available in all MPS2 and MPS2+ configurations.
The following figure shows the bit assignments.
31
0
Reserved
SWITCH[7:0]
78
0 0 0 0 0 0 0 0
Figure 4-3 SCC_CFG3 Register bit assignments
The following table shows the bit assignments.
Table 4-4 SCC_CFG3 Register bit assignments
Bits Name Function
[31:8] - Reserved. Do not write to these bits.
[7:0] SW[7:0] These bits indicate the state of the user switches:
• 0b0 Off
• 0b1 On
Related information
2.11 User switches and user LEDs on page 2-35
4.3 Register summary on page 4-62
4.4.5 SCC_CFG4 Register
The SCC_CFG4 Register characteristics are:
Purpose
Contains MPS2 and MPS2+ board revision information.
Usage constraints
The SCC_CFG4 Register is read-only.
Configurations
Available in all MPS2 and MPS2+ configurations.
The following figure shows the bit assignments.
31
0
Reserved
Board
revision
34
Figure 4-4 SCC_CFG4 Register bit assignments
The following table shows the bit assignments.
4 Programmers Model
4.4 SCC register descriptions
100112_0200_09_en Copyright © 2013–2016, 2018–2020 Arm Limited or its affiliates. All
rights reserved.
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