2.15 Debug and trace
This section describes the debug and trace systems on the MPS2 and MPS2+ FPGA Prototyping Boards.
This section contains the following subsections:
• 2.15.1 Overview of FPGA debug and trace systems on page 2-43.
• 2.15.2 F-JTAG on page 2-44.
• 2.15.3 P-JTAG on page 2-45.
• 2.15.4 4-bit Trace on page 2-45.
• 2.15.5 16-bit Trace on page 2-45.
• 2.15.6 Serial Wire Debug on page 2-45.
• 2.15.7 CMSIS-DAP FPGA debug on page 2-46.
2.15.1 Overview of FPGA debug and trace systems
The MPS2 and MPS2+ FPGA Prototyping Boards provide several debug and trace interfaces:
• P-JTAG processor debug.
• F-JTAG FPGA debug.
• 16-bit parallel Trace.
• 4-bit parallel Trace.
• Serial Wire Debug (SWD).
• CMSIS-DAP FPGA debug.
Note
• The availability of system debug depends on the design that you implement in the FPGA.
• The MPS2 and MPS2+ FPGA Prototyping Boards require Motherboard Configuration Controller
(MCC) firmware version 2.0.1 or later to support CMSIS-DAP.
The following diagram shows a simplified view of the F-JTAG, P-JTAG, Trace, SWD, and CMSIS-DAP
connections.
Caution
The total current limit for the four P‑JTAG connectors, JTAG 20, MICTOR 38, CoreSight 20, and
CoreSight 10 is 50mA.
2 Hardware Description
2.15 Debug and trace
100112_0200_09_en Copyright © 2013–2016, 2018–2020 Arm Limited or its affiliates. All
rights reserved.
2-43
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