Related information
4.3 Register summary on page 4-62
4.4.8 SCC_ID Register
The SCC_ID Register characteristics are:
Purpose
The MCC reads this register and uses the information to determine information about the design
in the FPGA that you can read through the MPS2 or MPS2+ FPGA Prototyping Board
SYS_CFG interface.
Usage constraints
The SCC_ID Register is Read-only.
Configurations
Available in all MPS2 and MPS2+ configurations.
The following figure shows the bit assignments.
31
0
Variant Revision
24 23
ANImplementer
20 19 16 15
Architecture
Figure 4-7 SCC_ID Register bit assignments
The following table shows the bit assignments.
Table 4-8 SCC_ID Register bit assignments
Bits Name Function
[31:24] Implementer Implementer ID. 0x41 = Arm.
[23:20] Variant Product variant or major revision number:
Note
This refers to the core or cluster image in the FPGA and is the x in rxpy
[19:16 IP Architecture Architecture. 0x04 = AHB
[15:4] AN Application Note number.
• 382 AN382: V2M-M0 Application Note
• 383 AN383: V2M-M0+ Application Note
• 384 AN384: V2M-M1 Application Note
• 385 AN385: V2M-M3 Application Note
• 386 AN386: V2M-M4 Application Note
• 387 AN387: V2M-M0 Design Start Application Note
• 399 AN399: V2M-M7 Application Note
• 400 AN400: V2M-M7 Application Note with CoreSight
[3:0] Revision Product revision or minor revision number.
Note
This refers to the core or cluster image in the FPGA and is the y in rxpy
Related information
4.3 Register summary on page 4-62
4 Programmers Model
4.4 SCC register descriptions
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