Table 2-1 MCC AC timing requirements for SCC interface
Variable Time
MCC Clock to output valid time: Tov -500ns
MCC Clock to output invalid time: Toh 500ns
MCC input setup time: Tis 500ns
MCC input hold time: Tih -500ns
Related information
2.11 User switches and user LEDs on page 2-35
4.3 Register summary on page 4-62
4.4 SCC register descriptions on page 4-63
2 Hardware Description
2.13 MCC FPGA serial interface
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