Camera Interface
2-20 Basler A500k Series
PRELIMINARY
The sensor outputs 10 Bits, but the two bits output from each ADC are dropped and only 8 bits of
data per pixel is transmitted. The digital shift function selects the bits to be dropped (see section
3.8).
Video Data Sequence for the A501k/kc
When the camera is not transmitting valid data, the frame valid and line valid bits sent on each
cycle of the pixel clock will be low. The camera can acquire a frame and, at the same time, send
the previous frame. It can also first acquire a frame and then send it. When Frame valid becomes
high, the camera starts to send valid data:
• On the pixel clock cycle where frame data transmission begins, the frame valid bit will
become high. Five pixel clocks later, the line valid bit will become high (if AOI Starting Col-
umn = 0).
• On the pixel clock cycle where data transmission for line one begins, the line valid bit will
become high. Two data streams are transmitted in parallel during this clock cycle. The first
pixel is the first pixel in the first data stream D_0. The second pixel is the first pixel in the sec-
ond data stream D_1. 8 bits will contain the data for each pixel.
• On the next cycle of the pixel clock, the line valid bit will be high. The third pixel is the second
pixel in the D_0 data stream. The fourth pixel is the second pixel in the D_1 data stream. 8
bits will contain the data for each pixel.
• On the next cycle of the pixel clock, the line valid bit will be high. The fifth pixel is the third
pixel in the D_0 data stream. The sixth pixel is the third pixel in the D_1 data stream. 8 bits
will contain the data for each pixel.
• This pattern will continue until all of the pixel data for each data stream for line one has been
transmitted. (A total of 640 cycles for the
A501k/kc.)
• Line valid becomes low for twenty pixel clocks.
• On the pixel clock cycle where data transmission for line two begins, the line valid bit will
become high. Two data streams are transmitted in parallel during this clock cycle. In each
data stream, 8 bits will contain the data for the first and second pixel of line number two.
• On the next cycle of the pixel clock, the line valid bit will be high. Two data streams are trans-
mitted in parallel during this clock cycle. In each data stream, 8 bits will contain the data for
the third and fourth pixel of line number two.
• On the next cycle of the pixel clock, the line valid bit will be high. Two data streams are trans-
mitted in parallel during this clock cycle. In each data stream, 8 bits will contain the data for
the fifth and sixth pixel of line number two.
• This pattern will continue until all of the pixel data for each data stream for line two has been
transmitted. (A total of 640 cycles.)
• After all of the pixels in line two have been transmitted, the line valid bit will become low for
twenty cycles indicating that valid data for line two is no longer being transmitted.
• The camera will continue to transmit pixel data for each line as described above until all of
the lines in the frame have been transmitted. After all of the lines have been transmitted, the
*
The data sequence outlined below, along with Figures 2-9 and 2-10, describe what
is happening at the inputs to the Channel Link transmitters in the camera.
Note that the timing used for sampling the data at the Channel Link receivers in the
frame grabber varies from device to device. On some receivers, data must be sam-
pled on the rising edge of the pixel clock (receive clock), and on others, it must be
sampled on the falling edge. Also, some devices are available which allow you to
select either rising edge or falling edge sampling. Please consult the data sheet for
the receiver that you are using for specific timing information.
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