Basler A504k - Page 35

Camera Interface
Basler A500k Series 2-21
PRELIMINARY
frame valid bit will become low at the same time as line valid indicating that a valid frame is
no longer being transmitted.
• Frame valid will remain low for at least 15 pixel clock cycles until the next frame starts.
Figure 2-9 shows the data sequence when the camera is operating in edge-controlled or level-
controlled exposure mode and Figure 2-10 shows the data sequence when the camera is
operating in programmable exposure mode.
Figure 2-9: 8 Bit Output Mode with Edge or Level-controlled Exposure for the A501k/kc
ExSync
Signal
Frame
Valid
Line
Valid
Line 1 Line 2 Line 1024
Pixel
Clock
(50 M H z)
min. 3 µs
0.1 µs
0.4 µs 12.8 µs
13.2 µs
0 µs
13.517 ms
D_0
Pixel Data
(8 bits)
1277 127913
1279
1
1277 12791
D_1
Pixel Data
(8 bits)
1278 128024
1280
2
1278 12802
3
4
..5
..5
1
12
2
20
20 1
12
2
20
20
This diagram assumes that the area of interest feature is not being used. With the area of interest feature enabled, the
number of pixels transferred could be smaller.