Basler A504k User Manual

Basic Operation and Features
Basler A500k Series 3-1
PRELIMINARY
3 Basic Operation and Features
3.1 Functional Description
BASLER A500k area scan cameras employ a CMOS-sensor chip which provides features such as
a full frame shutter, electronic exposure time control and anti-blooming. Exposure time is
controlled either internally via an internal sync signal (free-run mode) or externally via an external
trigger (ExSync) signal. The ExSync signal facilitates periodic or non-periodic pixel readout.
In any free-run mode, the camera generates its own internal control signal and the internal signal
is used to control exposure and charge read out. When operating in free-run, the camera outputs
frames continuously.
When exposure is controlled by an ExSync signal, exposure time can be either edge-controlled,
level-controlled or programmable. In edge-controlled mode, charge is accumulated from the rising
edge to the next rising edge of ExSync. The rising edge of ExSync also triggers the readout. In
level-controlled mode, charge is accumulated when the ExSync signal is low and a rising edge of
ExSync triggers the readout. In programmable mode, exposure time can be programmed to a
predetermined time period. In this case, exposure begins on the rising edge of ExSync and
accumulated charges are read out when the programmed exposure time ends.
The
A504k/kc has a special feature: In addition to sending video data to a framegrabber, it can be
output to an VGA monitor (640 x 480 pixels). In VGA exposure mode the camera generates its
own internal control signal and the internal signal is used to control exposure and charge read out.
The frame frequency is set to 60 Hz. The camera outputs frames continuously to the monitor and,
at the same time, to the Camera Link output.
At readout, all accumulated charges of all pixels are simultaneously transported from the light-
sensitive sensor elements (pixels) to the pixel memory (full frame shutter). There is a pixel
memory for each pixel. As a consequence, the camera can be exposed and read out at the same
time. The charges of the pixel memory are amplified. The pixel memories can be connected to a
bus. There is one bus for each vertical column. At the end of each bus, there is an analog/digital
converter (ADC).
For readout, the pixel memories can be addressed linewise by closing a switch that connects the
pixel memory of the addressed lines to the busses. Before the analog video data enters the ADC,
the offset is added, plus a value that corrects column fixed pattern noise. The analog video data
is digitized by a ten bit, Analog to Digital converter (ADC). The ADC’s reference value is used to
set the gain. The digitized video data then passes a digital 128 stage shift register, which outputs
10 x 10 Bit of data in parallel with each cycle. Then the 10 Bit data enters the digital shifter in the
FPGA, which selects the 8 bits out of the 10 bits output by the sensor. The next step of the data
flow is different in the
A504k/kc and the A501k/kc:
• In the
A504k/kc, the data is formatted to be output in 10 data streams in parallel (10 taps).

Basler A504k Specifications

General

Brand	Basler
Model	A504k
Category	Security Camera
Language	English