Broadcom BCM7405 - Page 129

2/24/2008 9T6WP
Preliminary Hardware Data Module BCM7405
06/29/07 Hardware Signal Descriptions
Broadcom Corporation
Document 7405-1HDM00-R Pin Definition Notations Page 1-115
Miscellaneous Signals – 125
1 2 - Extended Bus
Interface/Reset In/Out
RESETb STI PU 3.3 AP13 Hardware reset control
(GLOBAL RESET)
1 2 - Extended Bus
Interface/Reset In/Out
RESET_OUTb O 3.3 8 AK34 External reset control
(GLOBAL RESET)
1 2 - Extended Bus
Interface/Reset In/Out
NMIb STI PU 3.3 AM13 Power failure indicator (This
is a non maskable interrupt
to the MIPS)
1 2 - Extended Bus
Interface/Reset In/Out
FP_4SEC_RE
SETb
STI PU 3.3 AN13 Long Front Panel Reset
Input
1 16 - GPIO GPIO_000 STI/O 5 12 A16 Generic I/O port. Shared
with ENET_ACTIVITY /
ENET_LINK / Ext. IRQb_13
1 16 - GPIO GPIO_001 STI/O 5 12 C16 Generic I/O port. Shared
with ENET_LINK /
ENET_ACTIVITY / Ext.
IRQb_14
1 16 - GPIO GPIO_002 STI/O PD 3.3 8 AB34 Generic I/O port. Shared
with MII_RX_CLK / Ext.
IRQb_0 / EXT_GFX_09
1 16 - GPIO GPIO_003 STI/O PD 3.3 8 AB32 Generic I/O port. Shared
with MII_RX_EN /
UART_RXD_0 /
EXT_GFX_10 / Ext.
IRQb_5
1 16 - GPIO GPIO_004 STI/O PD 3.3 8 AA34 Generic I/O port. Shared
with MII_RXD_00 /
UART_TXD_0 /
EXT_GFX_11 / Ext.
IRQb_6
1 16 - GPIO GPIO_005 STI/O PD 3.3 8 AA33 Generic I/O port. Shared
with MII_RXD_01 /
UART_CTS_0 /
EXT_GFX_12 / Ext.
IRQb_7 / VEC_HSYNC_0
1 16 - GPIO GPIO_006 STI/O PD 3.3 8 AA32 Generic I/O port. Shared
with MII_RXD_02 /
UART_RTS_0 /
EXT_GFX_13 / Ext.
IRQb_8 / VEC_HSYNC_1
1 16 - GPIO GPIO_007 STI/O PD 3.3 8 Y33 Generic I/O port. Shared
with MII_RXD_03 /
UART_RXD_1 /
EXT_GFX_14 / Ext.
IRQb_9
1 16 - GPIO GPIO_008 STI/O PD 3.3 8 Y30 Generic I/O port. Shared
with MII_RX_ER /
UART_TXD_1 /
EXT_GFX_15 / Ext.
IRQb_10
Table 1-19: Pin Descriptions (Cont.)
# of
Pins
Orcad Schematic
Block
Label I/O Res.
Tol.
(V)
Drv.
(mA)
Loc. Description